UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer janet
Observer
451 Views
Registered: ‎07-12-2018

DDR3 DMC AXI Unaligned Data Read Potential Problem

Jump to solution

Hi Experts,

I used the DDR3 DMC IP v1.4.2 in my current project. But while doing the data reading, the observed behavior is different from what I do expect basing on the AXI protocol.

 

As shown in the first snapshot, for a 32-bits sized transfer, the second transfer starts from the middle of the 64-bits data. The 64-bits data used in the second transfer is the same with the first transfer.

 

But in my case, for a 32-bits sized transfer, the second transfer is supposed to base on the same 128-bits data readout for the first transfer at the memory location 0x5e2260. The first transfer(at the cursor) starts from 0x5e2264 and the second transfer should start from 0x5e2268 within the same 128-bits. But fact is the second transfer starts from 0x5e2278.

 

Does anyone know why the dmc works like this? Is this a bug or anything else?

 

Thanks a lot for your time!

Janet

v2捕获.PNGAXI protocol snapshotv3捕获.PNGILA waveform snapshot

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer janet
Observer
396 Views
Registered: ‎07-12-2018

Re: DDR3 DMC AXI Unaligned Data Read Potential Problem

Jump to solution

The device I am using is xcvu440-flga2892-1-c.

IP is DDR3 SDRAM (MIG) AXI4

You are right. I checked I did not click the AXI narrow burst option.

This should be the root cause.

It is not a default setting in v1.4.2 but an default setting in v1.4.4

Thanks a lot !!123.PNGAXI IP snapshot

0 Kudos
3 Replies
Explorer
Explorer
417 Views
Registered: ‎03-31-2016

Re: DDR3 DMC AXI Unaligned Data Read Potential Problem

Jump to solution

You are not specific about which device you are using and I don't know of any Xilinx IP called DMC.  So I will answer in general terms

The AXI specs you listed deal with Write data not reads and in general it is the responsibility of the Interconnect to do width conversion.  A slave device is not required to monitor the AxSIZE in that way, it just has to look at the WSTRB on a write.

A properly configured Interconnect should have recognized that the master side was doing a 2 beat 4-Byte request (8 bytes total) and that they slave supports a 16-Byte interface and converted it to a single beat transfer and then mapped the response bytes to the appropriate byte lanes.

The standard Xilinx memory IP (MIG) has a "Narrow Burst" option to treat this in a way that does not impact the content of the memory but it might still send the extra data on a read, the documentation is not great on that feature and I dont have much experience with it

0 Kudos
Highlighted
Observer janet
Observer
397 Views
Registered: ‎07-12-2018

Re: DDR3 DMC AXI Unaligned Data Read Potential Problem

Jump to solution

The device I am using is xcvu440-flga2892-1-c.

IP is DDR3 SDRAM (MIG) AXI4

You are right. I checked I did not click the AXI narrow burst option.

This should be the root cause.

It is not a default setting in v1.4.2 but an default setting in v1.4.4

Thanks a lot !!123.PNGAXI IP snapshot

0 Kudos
Observer janet
Observer
388 Views
Registered: ‎07-12-2018

Re: DDR3 DMC AXI Unaligned Data Read Potential Problem

Jump to solution
sorry in v1.4.4 it is still not the default setting. Need to click it.
0 Kudos