10-22-2010 03:38 AM
When I searched into the Virtex 6 datasheet for Jitter values for the GTX reference clock pins, there is no data found. But I got the reply from Xilinx (in webcase). In the reply, Xilinx has provided a phase noise values (in dBc/rtHz) for different frequencies.
Now I have to convert this phase noise to Jitter values ( in pS) to compare against the clock source jitter values. Hope Xilinx doesn't have any documents to get the jitter values from phase noise.
My question is,
Why direct jitter value (in pS) is not given in Xilinx datasheet ? (it is easy to compare against the clock datasheet if values are available)
Is there any easiest way to get the jitter values from phase noise values ?
10-25-2010 03:30 PM
I'm assuming you were given the numbers listed out in this answer record: http://www.xilinx.com/support/answers/38506.htm
The reason we have moved to specifying phase noise masks over peak-to-peak or RMS jitter numbers is that the amplitude of the phase noise over a variety of frequencies is very important when determining if there will be a negative impact to the jitter performance of the GTX.
If you are using an RMA or p-p number, all of the frequency information is lost. As an example, it is possible to have 2 clocks with similar RMS jitter values, one with very little noise in the range where the GTX will be effected and one with much higher noise in those frequencies. These could result in very different TX jitter output or RX jitter tolerance and you would have no idea since they had similar RMS values.
It may be a bit more difficult, but comparing the phase noise masks to the phase noise plots for your reference clock will ensure better performance out of your link. Hope this helps!