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Posts: 21
Registered: ‎05-29-2015

Virtex-6 Translate error


  I have generated a fir filter through System Generator,and import ngc into my ISE project. it has wrong:

ERROR:NgdBuild:604 - logical block
2_instance' with type 'fr_cmplr_v5_0_f9207259caf9fa52' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, case
mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'fr_cmplr_v5_0_f9207259caf9fa52' is not
supported in target 'virtex6'.

i do not know  where is wrong,Can you help me?

thank you !

Xilinx Employee
Posts: 3,051
Registered: ‎10-24-2013

Re: Virtex-6 Translate error

Hi @fanwei

Can you check if the target device is same for the FIR filter and the ISE project?

Looks likes the system generator target part is set to Virtex-5 and the ISE project is set to Virtex-6

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Posts: 21
Registered: ‎05-29-2015

Re: Virtex-6 Translate error

Hi, the target device in System Generator and ISE Project are  Virtex-6. 

I have change the generate language Verilog to VHDL, but it is has more error.


Virtex-6 Translate error