UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Highlighted
Observer
Posts: 18
Registered: ‎05-29-2015

Virtex-6 Translate error

Hi,

  I have generated a fir filter through System Generator,and import ngc into my ISE project. it has wrong:

ERROR:NgdBuild:604 - logical block
'user_define_module_top_inst/udm_lreg_core_inst/correlator_ctrl_i/nco_acc_cw_
i/ddc_cor_x0/pfir_631d5b704c/fir_compiler_5_0_4/fr_cmplr_v5_0_f9207259caf9fa5
2_instance' with type 'fr_cmplr_v5_0_f9207259caf9fa52' could not be resolved.
A pin name misspelling can cause this, a missing edif or ngc file, case
mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'fr_cmplr_v5_0_f9207259caf9fa52' is not
supported in target 'virtex6'.

i do not know  where is wrong,Can you help me?

thank you !

Moderator
Posts: 3,046
Registered: ‎10-24-2013

Re: Virtex-6 Translate error

Hi @fanwei

Can you check if the target device is same for the FIR filter and the ISE project?

Looks likes the system generator target part is set to Virtex-5 and the ISE project is set to Virtex-6

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Observer
Posts: 18
Registered: ‎05-29-2015

Re: Virtex-6 Translate error

Hi, the target device in System Generator and ISE Project are  Virtex-6. 

I have change the generate language Verilog to VHDL, but it is has more error.

 

Virtex-6 Translate error