I am experiencing a weird FIFO problem on Virtex-5. Basically when i try to drive the read enable inpurt port of a XILINX FIFO ipcore directly in a process, valid signal of FIFO goes high immediately at the same clock cycle as read enable signal.
However when i drive an internal signal in the process and assign this signal to read enable port of FIFO combinatorially, valid signal goes high one clock cycle later as it should.
XILINX FIFOs are driving me crazy. I can never place a XILINX FIFO in rtl and happily go with it. They have always been a problme to me.
Thanks for replies,
RTL - 1 (Driving read enable input port directly in process)
SIMULATION - 1
RTL - 2 (Driving read enable input port via internal signal)
SIMULATION - 2
Sim #2 is the expected?
Could be a delta delay race causing shoot thru, either in the FIFO or your stuff. is the fifo driven by "clk" , or by another signal driven by "clk"?
I would not recommend using "variables" because the ":=" assignment encodes the ongoing clock cycle while you are encoding the next clock cycle of all the other variables. Maybe what is being interpreted from this code is misleading & confusing. It could also have to do with the FIFO settings especially if you are using a dual clock FIFO with asynchronous logic.
My experience with Xilinx FIFOs is we get a 1 clock cycle latency when reading stuff from it, you are not talking about data specifically but you will probably have to take this into account.
I also tend to use the "AXI4S" interface and completely dropped the native interface out because I usually get the expected results more quickly.