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Observer matt_marti09
Observer
4,166 Views
Registered: ‎08-27-2012

wiring clock signals

I am getting repetetive data reads from a block RAM buffer.  I think it may be from the clock wiring I used.  In one instance I simply assign a clock in the following way:

 

clock1<= clock2

 

Is this bad practice?  I know that I will obviously have a cycle delay, but are there possible other problems and what type of buffer would I need if I do need one???

 

Thanks in advance!

 

Matt Martinez

Junior research Engineer

CALIT2 UCSD

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2 Replies
Historian
Historian
4,162 Views
Registered: ‎02-25-2008

Re: wiring clock signals


@matt_marti09 wrote:

I am getting repetetive data reads from a block RAM buffer.  I think it may be from the clock wiring I used.  In one instance I simply assign a clock in the following way:

 

clock1<= clock2

 

Is this bad practice?  I know that I will obviously have a cycle delay, but are there possible other problems and what type of buffer would I need if I do need one???

 

Thanks in advance!

 

Matt Martinez

Junior research Engineer

CALIT2 UCSD


Without seeing any more code, my expectation is that there's no delay inserted at all, and clock1 and clock2 are simply merged into one signal.

 

Why do you expect otherwise?

----------------------------Yes, I do this for a living.
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Observer matt_marti09
Observer
4,146 Views
Registered: ‎08-27-2012

Re: wiring clock signals

Hey bassman,

 

Thanks for the reply...The problem is that the clocks are used in seperate code blocks.  In the one code block, the data is read from a DDR3 and sent to a RAM buffer.  I would have used a FIFO but we are running low on memory resources of that type.  The data is then read from the RAM buffer at say clock1 frequency and sent to the other code block where clock2 is located. 

 

In this second code block, clock2 is the Ethernet clock and data is sent out to the computer via Ethernet. 

 

I am only testing at this point, and a counter is being used to send a count with every enable signal so that I should get one count data from every Ethernet package.  I am getting many repetitions like 1,1,2,3,4,4,5,6,7,8,8,8,9,10 but it isnt consistant and the count is only once every RAM enable.  I feel like I might be missing the data on the enable signal or that the clocks are not synced so that I am getting a timing error which is somehow causing a repeat of data....I'm really stuck here because it isn't skipping any counts.   Let me know if this makes any sense and if you would like to see any code...its a lot lol.  Thanks so much for your help!

 

Matt Martinez

Junior research Engineer

CALIT2 UCSD

 

 

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