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ejleiss
Participant
Participant
425 Views
Registered: ‎06-03-2019

Access Custom RAM module from Zynq

Hello,

I created a RAM block module that I am saving data into on my Arty Z7-20.  I would like to access this data in the RAM buffer using the Zynq and save it to SD card.  I already have the SD card read/write working, but I am not exactly sure how to access the RAM buffer using the Zynq.  I have attached the RAM block VHDL below.  I am sure I need to create a custom IP block on my block diagram and use the AXI bus for this, but I was hoping for some more info on where to point to in order to get this working.

Thanks for any information.

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4 Replies
stephenm
Xilinx Employee
Xilinx Employee
360 Views
Registered: ‎09-12-2007

Yes, you will need to have an AXI interface. There is a create ip GUI in Vivado that you can use. If you create a AXI interface it will actually create a template with a register and BRAM that you can use as a reference.

This default IP might be good enough as is for your use case.

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ejleiss
Participant
Participant
356 Views
Registered: ‎06-03-2019

So if I am understanding you correctly, I should use the IP creator GUI to create custom IP of my RAM module which will in tern add the AXI interface template?  I have created custom IP before with axi interfaces, but only with something small like an LED or a single Byte of data.  I guess my real question is, what would I port map my RAM to in the IP editor since it will eventually be fairly large (much larger than a single byte).  Thanks for your response.

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stephenm
Xilinx Employee
Xilinx Employee
343 Views
Registered: ‎09-12-2007

The tool will create an IP with memory and register access. So, you need to use this as a template. However, depending on your design needs you might be able to use as is?

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dgisselq
Scholar
Scholar
306 Views
Registered: ‎05-21-2015

@ejleiss ,

If you use the create IP GUI approach, whatever you do--don't use the IP.  Lots of users have been here complaining about their designs locking up hard after using the Xilinx generated IP.  It's horribly broken.  I reported the bugs in the AXI-lite slave example in 2018, and in the AXI full slave example in mid 2019.  As of Vivado 2020.2, Xilinx has yet to fix them.

Here's a better block RAM IP you can use and/or modify.  Not only will it work, but you'll even get better performance as well.

Dan

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