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sqtyale
Visitor
Visitor
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Registered: ‎01-02-2020

Can we make Vitis ignore timing violations?

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According to the Vitis document, v++ will return an error if the RTL kernel does not pass timing requirements. However, we may need to integrate some timing-violated modules into the whole project. Is it possible to turn this error into a warning so that Vitis ignores the timing violation?

Thanks!

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randyh
Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎01-04-2013
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randyh
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎01-04-2013