cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
fpgabob
Visitor
Visitor
852 Views
Registered: ‎05-07-2018

Differences between 4DDR and 1DDR platform

Jump to solution

Hello,

 

I am a new user in FPGA developments using OpenCL. Could someone explain the difference between 4DDR and 1 DDR platform on Virtex FPGAs? 

 

If I use the 1DDR configuration, does it mean that I have less memory, but more resources to implement additional logic?

What is the trade-off?

 

Is there a documentation clarifying the differences?

 

Thanks for the clarification!

 

FpgaBob

0 Kudos
Reply
1 Solution

Accepted Solutions
evant
Xilinx Employee
Xilinx Employee
1,033 Views
Registered: ‎09-08-2011

Hi FPGA bob,

 

   Is this in context of the Dynamic 5.0 DSAs?

 

For the Dynamic DSAs, as you use fewer DDRs you will have less total memory to work with, and you will have less potential bandwidth. 4DDRs allow you to separate read/writes per bank, but if you don't need the extra DDRs the Dynamic DSAs allow the logic that is needed for these additional controllers to be removed allowing more space for the end users designs, and likely faster build times and performance.

 

These advantages are covered in the release notes: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1238-sdx-rnil.pdf

 

And in Chapter 2:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1164-sdaccel-platform-development.pdf

 

Evan

If at first you don't succeed, try redefining success?

View solution in original post

1 Reply
evant
Xilinx Employee
Xilinx Employee
1,034 Views
Registered: ‎09-08-2011

Hi FPGA bob,

 

   Is this in context of the Dynamic 5.0 DSAs?

 

For the Dynamic DSAs, as you use fewer DDRs you will have less total memory to work with, and you will have less potential bandwidth. 4DDRs allow you to separate read/writes per bank, but if you don't need the extra DDRs the Dynamic DSAs allow the logic that is needed for these additional controllers to be removed allowing more space for the end users designs, and likely faster build times and performance.

 

These advantages are covered in the release notes: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1238-sdx-rnil.pdf

 

And in Chapter 2:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug1164-sdaccel-platform-development.pdf

 

Evan

If at first you don't succeed, try redefining success?

View solution in original post