I am using Vitis to develop a C/C++ application which offloads to an Alveo U250 FPGA one kernel developd in C + HLS.
I want to instantiate 4 different CUs of the same kernel, but I am having congestion problems causing routing errors in the implementation design phase. I reduced the kernel complexity to be able to complete the implementation and then tried to study what is going on opening the Vivado project.
As can be seen from the attached image (where the congestion metric is plotted), one of the 4 CUs has an higher congestion level than the others.
Shouldn't the 4 SLRs be exactly the same? And if it is the case, given that also the kernel is the same, why do I have different congestion levels in the different CUs?
The high congestion area seems to be both in the dynamic region and static region, but as far as I understood the kernel code should be mapped only in the dynamic region, how can I affect the static region congestion?
p.s. I can also see in this image a large gray boundle net connecting the static region with the upper SLR. What is this?