cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
1,139 Views
Registered: ‎05-11-2018

Emulation SW error with custom HLS function

Jump to solution

I modified the mat_mul example , and add a same function ’mmult’ but using C instead . 

the emulation_sw is stuck  and the info is like bellow :

but  the emulation-hw and sytem  run successful. 

Does anyone know why ?  

 

> Found Platform
> Platform Name: Xilinx
> XCLBIN File Name: mmult
> INFO: Importing ./mmult.xclbin
> Loading: './mmult.xclbin'
> Found Platform
> Platform Name: Xilinx
> XCLBIN File Name: mmult_c   // the hls_c kernel named mmult_c 
> INFO: Importing ./mmult_c.xclbin
> Loading: './mmult_c.xclbin'   
> TIMEOUT :: S_AXI_CONTROL remap  entry is absent in xmlbin  

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
981 Views
Registered: ‎11-04-2010

Hi, @yanhan ,

The root cause of the issue in SW-Emulation is the incorrect setting of HLS kernel interface.

The control signal of port in1, in2, out are not set.

The correct code should be:

#pragma HLS INTERFACE s_axilite port=return bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=dim bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=in1 bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=in2 bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=out bundle=s_axi_control
#pragma HLS INTERFACE m_axi port=in1 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=in2 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=m_axi

You can also refer to content in UG1023

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

t1.png
t2.png
8 Replies
Highlighted
Moderator
Moderator
1,109 Views
Registered: ‎11-04-2010

Hi, @yanhan ,

Which versoin SDAccel are you using?

Could you provide the code of your  ’mmult' to reproduce the issue?

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
1,105 Views
Registered: ‎05-11-2018

hi, @hongh, the code as below. 

the version is sdx2018.2 ( not 2018.2 xdf ) .

#define MAX_SIZE 64
extern "C"
{
void mmult(  int* in1,  //Read-only input matrix1
	int* in2,  //Read-only input matrix2
	int* out,  //Output matrix
	int dim             //One dimension of the matrix
          )
{
#pragma HLS INTERFACE s_axilite port=return bundle=axi_ctrl
#pragma HLS INTERFACE s_axilite port=dim bundle=axi_ctrl
#pragma HLS INTERFACE m_axi port=in1 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=in2 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=m_axi

	int src1[MAX_SIZE][MAX_SIZE] , src2[MAX_SIZE][MAX_SIZE] ;
#pragma HLS ARRAY_PARTITION variable=src1 complete dim=2
#pragma HLS ARRAY_PARTITION variable=src2 complete dim=1

	int dst[MAX_SIZE][MAX_SIZE] ;
#pragma HLS ARRAY_PARTITION variable=dst complete dim=2

//#pragma HLS DATAFLOW

	read_src1: for(int idx=0, i=0, j=0 ; idx< dim * dim ; idx++){
#pragma HLS PIPELINE rewind
		if(j >= dim) {
			i++ ;
			j= 0 ;
		}
		src1[i][j] = in1[idx] ;
//		cout << "idx= "<<idx << ", in1[idx]= "<< in1[idx] << ", src1= "<< src1[i][j] << ", i,j = "<<i << ", "<<j << endl ;
		j++ ;
	}
	read_src2: for(int idx=0, i=0, j=0 ; idx< dim * dim ; idx++){
#pragma HLS PIPELINE rewind 
		if(j >= dim) {
			i++ ;
			j= 0 ;
		}
		src2[i][j] = in2[idx] ;
//		cout << "idx= "<<idx << ", in2[idx]= "<< in2[idx] << ", src2= "<< src2[i][j]<< ", i,j = "<<i << ", "<<j << endl ;
		j++ ;
	}

	compute: for(int i=0; i<dim ; i++){
		for(int j=0 ; j<dim; j++){
			dst[i][j] = 0 ;
#pragma HLS PIPELINE rewind
			for(int k=0; k<MAX_SIZE ; k++){
#pragma HLS UNROLL
				dst[i][j] += src1[i][k] * src2[k][j] ;
			}
		}
	}
	write_dst: for(int idx=0, i=0, j=0 ; idx< dim * dim ; idx++){
#pragma HLS PIPELINE rewind
		if(j >= dim) {
			i++ ;
			j=0 ;
		}
		out[idx] = dst[i][j] ;
		j++ ;
	}
}

}
0 Kudos
Highlighted
Contributor
Contributor
1,070 Views
Registered: ‎05-11-2018

hi, @hongh,
Is there any news about the problem? have you reproduced it ?

0 Kudos
Highlighted
Moderator
Moderator
1,060 Views
Registered: ‎11-04-2010

Hi, @yanhan ,

Currently the issue has been reproduced in SDx 2018.2. 

 

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Moderator
Moderator
982 Views
Registered: ‎11-04-2010

Hi, @yanhan ,

The root cause of the issue in SW-Emulation is the incorrect setting of HLS kernel interface.

The control signal of port in1, in2, out are not set.

The correct code should be:

#pragma HLS INTERFACE s_axilite port=return bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=dim bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=in1 bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=in2 bundle=s_axi_control
#pragma HLS INTERFACE s_axilite port=out bundle=s_axi_control
#pragma HLS INTERFACE m_axi port=in1 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=in2 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=m_axi

You can also refer to content in UG1023

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

t1.png
t2.png
Highlighted
Contributor
Contributor
947 Views
Registered: ‎05-11-2018

Hi, @hongh

Thanks, the issue is really caused by the lack of setting the control interface. 

But , I found that the bundle name can only be set as 'control' as the example in  ug1023. 

That doesnot seem reasonable. Actually ug1023 only specifies the setting syntax ,not the bundle name. 

#pragma HLS INTERFACE s_axilite port=return bundle=control   // should not be another name, 
#pragma HLS INTERFACE s_axilite port=dim bundle=control      // Or  Emulation-SW can't work 
#pragma HLS INTERFACE s_axilite port=in1 bundle=control
#pragma HLS INTERFACE s_axilite port=in2 bundle=control
#pragma HLS INTERFACE s_axilite port=out bundle=control
#pragma HLS INTERFACE m_axi port=in1 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=in2 offset=slave bundle=m_axi
#pragma HLS INTERFACE m_axi port=out offset=slave bundle=m_axi
0 Kudos
Highlighted
Moderator
Moderator
937 Views
Registered: ‎11-04-2010

Hi, @yanhan ,

It' a limitation in SDx 2018.2. 

You can use arbitary bundle name in SDx 2018.3(The new version of SDx).

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Contributor
Contributor
929 Views
Registered: ‎05-11-2018
Hi, @hongh,
Got it , thank you.
0 Kudos