Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎09-09-2019

Error meet when package the xo file to xclbin

Hi I am working on the sample project of :

I build the sample project under command line,  and then using vitis_hl to open the project, created a xo file, then when I am trying to create an xclbin file I meet below error:

$v++ -t hw --platform xilinx_u200_xdma_201830_2 --link DUT_FUNC.xo -o'sha256.hw.xclbin'


ERROR: [KernelCheck 83-117] '' kernel.xml indicates the existence of port MSG_STRM.V, which does not exist
ERROR: [SYSTEM_LINK 82-63] Error generating intermediate file /../xilinx_com_hls_DUT_FUNC_1_0/DUT_FUNC.fcnmap.xml
ERROR: [SYSTEM_LINK 82-78] Unable to create function map for HLS kernel DUT_FUNC
ERROR: [SYSTEM_LINK 82-84] Unable to process .xo file: /../src/kernel/DUT_FUNC.xo
ERROR: [SYSTEM_LINK 82-66] Error processing .xo files
ERROR: [SYSTEM_LINK 82-100] Error processing object files, exiting

Additionally, I find some post mentioned the issue would be relevant to the interface. In vitis_hls document I can find these descriptions:

When specifying open_solution -flow_target vitis, or enabling the Vitis Kernel Flow in the GUI, Vitis HLS implements interface ports using the AXI standard as described in Port Level I/O: AXI4 Interface Protocol, and Using AXI4 Interfaces.

As the interface of this C++ sha256 kernel defines all hls::stream type interface, which is stream but not usual AXI interface, does that mean the vitis_hls implementation phase will generate the .xo target by warpping up the interface with AXI port??


0 Kudos
0 Replies