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nirdhish
Contributor
Contributor
380 Views
Registered: ‎08-26-2018

HBM global addressing using Vitis custom flow - Alveo u280 card

Hi,
I am running a custom RTL with an axi master port connected to HBM[0] port. According to the HBM IP documentation, I must be able to access the entire HBM memory space (albeit with higher latency and lower bandwidth) from this single port. While the simulation passes without any errors, I am getting this error in hardware emulation run.

 

ERROR::[ 1 ] .emu_wrapper.emu_i.hmss_0.inst.xtlm_intercon_kernel.inst.icn.impl: Transaction from Target with Address 0x10000000 cannot be routed 

Through vitis analyser and .xclbin.info file, I came to know that the accessible range from HBM[0] port is 0x1000_0000.

 

 

This is what I find in .xclbin.info
Name: HBM[0] Index: 0 Type: MEM_DDR4 Base Address: 0x0 Address Size: 0x10000000 Bank Used: Yes Name: HBM[1] Index: 1 Type: MEM_DDR4 Base Address: 0x10000000 Address Size: 0x10000000 Bank Used: Yes

 

This is what I find in Vitis link summary.
HBM[0] DDR4 true 0x40000 0x0 HBM[1] DDR4 true 0x40000 0x1000_0000

That error makes sense now. But, Is it possible to have global access to HBM memory space from HBM[0]? If yes, what changes should I make to my project? As far as the host code is concerned, I am using the default code generated by Vitis.

Thank you for your help.

 

 

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bchebrol
Xilinx Employee
Xilinx Employee
317 Views
Registered: ‎06-04-2018

Hi @nirdhish ,

you can use the following HBM example for reference : 

https://github.com/Xilinx/Vitis_Accel_Examples/tree/master/host/hbm_bandwidth

Regards,
Vishnu
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