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Participant
Participant
402 Views
Registered: ‎04-01-2019

Hardware kernel development and register access

Hi,
I'm working on a custom hardware kernel and I have some questions:

First of all, I would ask about the Xilinx Runtime commands. In 2018.3 docummentation I saw the 'xclWrite' command for register access. But it was marked as deprecated. I have found a Git commit, that the new name is 'xclRegWrite', but in current (2020.1) documentation both commands are missing and there is no information, if register access is supported. So is it just missing in documentation or not supported at all?

Secondly, I have a question about the hardware kernel. I would like to create a hardware kernel and share it as .xo file. I have read in UG1393 that the IP has to have some specific registers (control, interrupt etc.), that ports have to have specified names like s_axi_control. So my question is, can I use the same AXI4 Lite control bus to access the IP internal register space? And for Alveo cards: can I use this bus like the IP would be connected to a CPU to read/write e.g. my IP's FIFO?

Thirdly, I have a hardware related question. Can I use a Zynq board with my custom platform project and kernel in the same way as it is written about the Alveo cards? I mean, will I be able to create a platform consisting only of the Zynq, processor system reset and AXI interconnect, and than add for v++ compillation the prepared .xo file?

Thank you for the answer!

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Moderator
Moderator
379 Views
Registered: ‎09-12-2007

For accessing the registers, once the interface is memory mapped, then you can use devmem to access them.

Yes, you can create your custom platform however you want. Once you provide the metadata to the Vitis using the PFM properties

There is a good article here on how to create the platform for zynq:

https://www.hackster.io/news/microzed-chronicles-microzed-zynq-7000-vitis-platform-creation-df25e1054fb6

Participant
Participant
366 Views
Registered: ‎04-01-2019

Thank you, the article is very helpful. The key I was missing was the "Platform Interfaces" option in Vivado.

So summing up, to use the accelerated flow I have to use Petalinux. There is no way to do it in bare-metal?

And if I will be able to use devmem, I should also be able to use just mmap() ?

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Moderator
Moderator
362 Views
Registered: ‎09-12-2007

If you want to use the accelerated flow, then you need an XRT in the rootfs in Linux. The supported way to do this is to use Petalinux

Participant
Participant
297 Views
Registered: ‎04-01-2019

So we come back to the beginning. Please answer my question about Xilinx Runtime XRT register access:

"In 2018.3 docummentation I saw the 'xclWrite' command for register access. But it was marked as deprecated. I have found a Git commit, that the new name is 'xclRegWrite', but in current (2020.1) documentation both commands are missing and there is no information, if register access is supported. So is it just missing in documentation or not supported at all?"

 

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