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Newbie
Newbie
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Registered: ‎03-19-2020

How to compile a bare metal driver with Vitis 2019.2 ?

How can I build the bare metal example application
in ${VITIS_ROOT}/Vitis/2019.2/data/embeddedsw/XilinxProcessorIPLib/drivers/emacps_v3_10/examples with Vitis for the board ZCU104 ?

Which GemVersion have the Ethernet-Ports in the board ZCU104 ?
(My program reads out 7 - is that right ?)

In procedure XEmacPsClkSetup (Line 1379 in xemacps_example_intr_dma.c):
What is a SLCR ? (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf referenced but not defined ?)

In xemacps_example_intr_dma.c:150 is XPAR_PS7_SLCR_0_S_AXI_BASEADDR referenced.
Searching it returns
embeddedsw$ find . -name 'xpara*' -exec grep -Hn XPAR_PS7_SLCR_0_S_AXI_BASEADDR {} \;
./lib/sw_apps/zynq_fsbl/misc/zed/xparameters.h:217:#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
./lib/sw_apps/zynq_fsbl/misc/zc702/xparameters.h:238:#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
./lib/sw_apps/zynq_fsbl/misc/zc706/xparameters.h:217:#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000

Where it is defined for ZCU104 ?

 

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