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sejin
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Registered: ‎02-24-2021

How to increase the span of Pblock 'pblock_dynamic_SLR1'

I'm using vitis 2020.1 and working on platform xilinx_u200_xdma_201830_2.

During the build process, I am getting the following error.

ERROR: [VPL UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Pblock pblock_dynamic_SLR1 (This design requires more RAMB18 and RAMB36/FIFO cells than are available in Pblock 'pblock_dynamic_SLR1'. This design requires 841 of such cell types but only 840 compatible sites are available in Pblock 'pblock_dynamic_SLR1'. Please consider increasing the span of Pblock 'pblock_dynamic_SLR1' or removing cells from it.)
ERROR: [VPL 4-23] Error(s) found during DRC. Placer not run.
ERROR: [VPL 60-773] In '/home/user1/Documents/vitis_lab/training/pybind_commandline_flow/lab/build/hw/link/vivado/vpl/runme.log', caught Tcl error: problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/user1/Documents/vitis_lab/training/pybind_commandline_flow/lab/build/hw/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/user1/Documents/vitis_lab/training/pybind_commandline_flow/lab/build/hw/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker

I'm assuming the following errors are occurring due to the first error.

I would like to increase the span of Pblock 'pblock_dynamic_SLR1' to solve this issue.

Is there a way to do so?

Also, any other way to solve this issue is fine.

Thanks in advance

 

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