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guy.berger
Observer
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Registered: ‎10-31-2019

Migrating app from SDK to Vitis - Can't program flash

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Hello,

We recently migrated our code from Xilinx SDK 2015.4 & Vivado 2015.4 to Vitis & Vivado 2019.2. (I'll note that we do not have the following problem when using version 2015.4).

We are developing over a custom board that has Zynq-7000.

Followed by minor changes in the code to adapt to the new environment it's all working fine but only via JTAG debugging (in Vitis).

We are having trouble booting from flash after programming it.

Image is generated via the "Grenerate Boot image" tool and we load 3 files in that order: fsbl.elf, bitstream.bit, application.elf.

We then use the "Program flash" tool and provide the generated .mcs and the fsbl file (we tried to also create boot image without fsbl then add when programing flash asks for it).

Debugging is working with a .tcl initialization and also with our fsbl file initialization, however the application doesn't work after we program the flash (successfuly) and boot from it.

Are there Vitis specific changes need to be done in order to support the flash programming (that differ from the SDK)?

Any pointers and assistance will be much appretiated!

----------------------------

Programming log:

****** Xilinx Program Flash
****** Program Flash v2019.2 (64-bit)
**** SW Build 2708876 on Wed Nov 6 21:40:23 MST 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


WARNING: Failed to connect to hw_server at TCP:127.0.0.1:3121
Attempting to launch hw_server at TCP:127.0.0.1:3121

Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC10-00001716403501
Device 0: jsn-DLC10-00001716403501-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory
Using default mini u-boot image file - C:/Xilinx/Vitis/2019.2/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x001772C0 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x001772C0
===== mrd->addr=0xF8000100, data=0x0001A008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008
===== mrd->addr=0xF8000120, data=0x1F000200 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000200
===== mrd->addr=0xF8000118, data=0x001F42C0 =====
READ: IO_PLL_CFG (0xF8000118) = 0x001F42C0
===== mrd->addr=0xF8000108, data=0x00014008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x00014008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B

 


U-Boot 2019.01-00203-g2229398 (Aug 26 2019 - 04:42:15 -0600)

 

Model: Zynq CSE QSPI SINGLE Board

DRAM: 256 KiB

WARNING: Caches not enabled

In: dcc

Out: dcc

Err: dcc

Zynq> sf probe 0 0 0


Warning: SPI speed fallback to 100 kHz

SF: Detected n25q128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB

Zynq> Sector size = 65536.
f probe 0 0 0


Performing Erase Operation...
sf erase 0 450000


SF: 4521984 bytes @ 0x0 Erased: OK

Zynq> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 44 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 20000


device 0 offset 0x0, size 0x20000

SF: 131072 bytes @ 0x0 Written: OK

Zynq> sf write FFFC0000 20000 20000


device 0 offset 0x20000, size 0x20000

SF: 131072 bytes @ 0x20000 Written: OK

Zynq> sf write FFFC0000 40000 20000


device 0 offset 0x40000, size 0x20000

SF: 131072 bytes @ 0x40000 Written: OK

Zynq> sf write FFFC0000 60000 20000


device 0 offset 0x60000, size 0x20000

SF: 131072 bytes @ 0x60000 Written: OK

Zynq> sf write FFFC0000 80000 20000


device 0 offset 0x80000, size 0x20000

SF: 131072 bytes @ 0x80000 Written: OK

Zynq> sf write FFFC0000 A0000 20000


device 0 offset 0xa0000, size 0x20000

SF: 131072 bytes @ 0xa0000 Written: OK

Zynq> sf write FFFC0000 C0000 20000


device 0 offset 0xc0000, size 0x20000

SF: 131072 bytes @ 0xc0000 Written: OK

Zynq> 20%...sf write FFFC0000 E0000 20000


device 0 offset 0xe0000, size 0x20000

SF: 131072 bytes @ 0xe0000 Written: OK

Zynq> sf write FFFC0000 100000 20000


device 0 offset 0x100000, size 0x20000

SF: 131072 bytes @ 0x100000 Written: OK

Zynq> sf write FFFC0000 120000 20000


device 0 offset 0x120000, size 0x20000

SF: 131072 bytes @ 0x120000 Written: OK

Zynq> sf write FFFC0000 140000 20000


device 0 offset 0x140000, size 0x20000

SF: 131072 bytes @ 0x140000 Written: OK

Zynq> sf write FFFC0000 160000 20000


device 0 offset 0x160000, size 0x20000

SF: 131072 bytes @ 0x160000 Written: OK

Zynq> sf write FFFC0000 180000 20000


device 0 offset 0x180000, size 0x20000

SF: 131072 bytes @ 0x180000 Written: OK

Zynq> sf write FFFC0000 1A0000 20000


device 0 offset 0x1a0000, size 0x20000

SF: 131072 bytes @ 0x1a0000 Written: OK

Zynq> sf write FFFC0000 1C0000 20000


device 0 offset 0x1c0000, size 0x20000

SF: 131072 bytes @ 0x1c0000 Written: OK

Zynq> sf write FFFC0000 1E0000 20000


device 0 offset 0x1e0000, size 0x20000

SF: 131072 bytes @ 0x1e0000 Written: OK

Zynq> sf write FFFC0000 200000 20000


device 0 offset 0x200000, size 0x20000

SF: 131072 bytes @ 0x200000 Written: OK

Zynq> 50%...sf write FFFC0000 220000 20000


device 0 offset 0x220000, size 0x20000

SF: 131072 bytes @ 0x220000 Written: OK

Zynq> sf write FFFC0000 240000 20000


device 0 offset 0x240000, size 0x20000

SF: 131072 bytes @ 0x240000 Written: OK

Zynq> sf write FFFC0000 260000 20000


device 0 offset 0x260000, size 0x20000

SF: 131072 bytes @ 0x260000 Written: OK

Zynq> sf write FFFC0000 280000 20000


device 0 offset 0x280000, size 0x20000

SF: 131072 bytes @ 0x280000 Written: OK

Zynq> sf write FFFC0000 2A0000 20000


device 0 offset 0x2a0000, size 0x20000

SF: 131072 bytes @ 0x2a0000 Written: OK

Zynq> sf write FFFC0000 2C0000 20000


device 0 offset 0x2c0000, size 0x20000

SF: 131072 bytes @ 0x2c0000 Written: OK

Zynq> sf write FFFC0000 2E0000 20000


device 0 offset 0x2e0000, size 0x20000

SF: 131072 bytes @ 0x2e0000 Written: OK

Zynq> 70%...sf write FFFC0000 300000 20000


device 0 offset 0x300000, size 0x20000

SF: 131072 bytes @ 0x300000 Written: OK

Zynq> sf write FFFC0000 320000 20000


device 0 offset 0x320000, size 0x20000

SF: 131072 bytes @ 0x320000 Written: OK

Zynq> sf write FFFC0000 340000 20000


device 0 offset 0x340000, size 0x20000

SF: 131072 bytes @ 0x340000 Written: OK

Zynq> sf write FFFC0000 360000 20000


device 0 offset 0x360000, size 0x20000

SF: 131072 bytes @ 0x360000 Written: OK

Zynq> sf write FFFC0000 380000 20000


device 0 offset 0x380000, size 0x20000

SF: 131072 bytes @ 0x380000 Written: OK

Zynq> sf write FFFC0000 3A0000 20000


device 0 offset 0x3a0000, size 0x20000

SF: 131072 bytes @ 0x3a0000 Written: OK

Zynq> sf write FFFC0000 3C0000 20000


device 0 offset 0x3c0000, size 0x20000

SF: 131072 bytes @ 0x3c0000 Written: OK

Zynq> sf write FFFC0000 3E0000 20000


device 0 offset 0x3e0000, size 0x20000

SF: 131072 bytes @ 0x3e0000 Written: OK

Zynq> sf write FFFC0000 400000 20000


device 0 offset 0x400000, size 0x20000

SF: 131072 bytes @ 0x400000 Written: OK

Zynq> sf write FFFC0000 420000 20000


device 0 offset 0x420000, size 0x20000

SF: 131072 bytes @ 0x420000 Written: OK

Zynq> 100%
sf write FFFC0000 440000 5210


device 0 offset 0x440000, size 0x5210

SF: 21008 bytes @ 0x440000 Written: OK

Zynq> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 104 sec.

Flash Operation Successful

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denist
Xilinx Employee
Xilinx Employee
1,225 Views
Registered: ‎10-11-2011

I am not sure what this one means:

"we tried to also create boot image without fsbl then add when programing flash asks for it"

The bootimage MUST always contain the FSBL is it. The FSBL required for Flash Programming is only used to initialize the system in order to be able to program the flash.

Anyway, the console seems to to showing the Flash Programming is succesfull (You can add the verify step to double check the flash content).

I have to assume there's something NOT right with the image itself. Can I see the .bif?

Also, after a failing boot there's a register you can read with the error code.

BOOTROM_ERROR_CODE in REBOOT_STATUS

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2 Replies
denist
Xilinx Employee
Xilinx Employee
1,226 Views
Registered: ‎10-11-2011

I am not sure what this one means:

"we tried to also create boot image without fsbl then add when programing flash asks for it"

The bootimage MUST always contain the FSBL is it. The FSBL required for Flash Programming is only used to initialize the system in order to be able to program the flash.

Anyway, the console seems to to showing the Flash Programming is succesfull (You can add the verify step to double check the flash content).

I have to assume there's something NOT right with the image itself. Can I see the .bif?

Also, after a failing boot there's a register you can read with the error code.

BOOTROM_ERROR_CODE in REBOOT_STATUS

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

xuantran
Contributor
Contributor
834 Views
Registered: ‎04-11-2019

Could you share what was the solution of this problem?

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