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kennetho
Xilinx Employee
Xilinx Employee
11,703 Views
Registered: ‎02-23-2016

Multi DDR bank support

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Hi,

 

I have an sdaccel project with HLS kernel. I'm attempting to make use of the new multi ddr bank functionality to increase memory bandwidth. I get a link error: 

 

INFO: [XOCC 60-629] Linking for hardware target
INFO: [XOCC 60-423] Target device: xilinx:adm-pcie-ku3:2ddr:2.1
INFO: [XOCC 60-242] Creating kernel: 'smithwaterman'
INFO: [XOCC 60-694] Validating user connections (map_connect)...
INFO: [XOCC 60-690] User connection 'kernel|k1|M_AXI_GMEM0' is valid
INFO: [XOCC 60-690] User connection 'core|OCL_REGION_0|M00_AXI' is valid
INFO: [XOCC 60-690] User connection 'kernel|k1|M_AXI_GMEM1' is valid
INFO: [XOCC 60-690] User connection 'core|OCL_REGION_0|M01_AXI' is valid
INFO: [XOCC 60-690] User connection 'kernel|k1|M_AXI_GMEM2' is valid
INFO: [XOCC 60-690] User connection 'core|OCL_REGION_0|M00_AXI' is valid
INFO: [XOCC 60-251] Hardware accelerator integration...
....
ERROR: [XOCC 60-704] Integration error, problem with OCL region: Found connection from kernel 'k1/M_AXI_GMEM1' to multiple master interfaces
ERROR: [XOCC 60-626] Kernel link failed to complete
ERROR: [XOCC 60-703] Failed to finish linking

 

Relevant code snippets:

 

From the kernel:

 

 

void smithwaterman(ap_uint<NUM_ELEM_BITS>  *g_query, ap_uint<NUM_ELEM_BITS> *g_database, ap_int<512> *directionMatrix)
  {
  #pragma HLS INTERFACE m_axi port=g_query offset=slave bundle=gmem0                                                                                                                          
  #pragma HLS INTERFACE m_axi port=g_database offset=slave bundle=gmem1
  #pragma HLS INTERFACE m_axi port=directionMatrix offset=slave bundle=gmem2

  #pragma HLS INTERFACE s_axilite port=g_query bundle=control
  #pragma HLS INTERFACE s_axilite port=g_database bundle=control
  #pragma HLS INTERFACE s_axilite port=directionMatrix bundle=control
  #pragma HLS INTERFACE s_axilite port=return bundle=control

...
...

}

  From the host;

 

    cl_mem_ext_ptr_t input_a_ext;
    cl_mem_ext_ptr_t input_b_ext;
    cl_mem_ext_ptr_t output_ext;
    
    input_a_ext.flags = XCL_MEM_DDR_BANK0;                                                                                                                                                    
    input_a_ext.obj =  query_param;
    input_a_ext.param = 0;
    
    input_b_ext.flags = XCL_MEM_DDR_BANK1;
    input_b_ext.obj =  database_param;
    input_b_ext.param = 0;
    
    output_ext.flags = XCL_MEM_DDR_BANK0;
    output_ext.obj =  results2;
    output_ext.param = 0;

  
  input_a = clCreateBuffer(context,  CL_MEM_READ_ONLY | CL_MEM_EXT_PTR_XILINX,  sizeof(unsigned int) * N/16, NULL, NULL);
  input_b = clCreateBuffer(context,  CL_MEM_READ_ONLY | CL_MEM_EXT_PTR_XILINX,  sizeof(unsigned int) * (M + 2*(N - 1))/16, NULL, NULL);
  output = clCreateBuffer(context, CL_MEM_WRITE_ONLY | CL_MEM_EXT_PTR_XILINX, sizeof(char)* 256*(N+M-1), NULL, NULL);

From the tcl:

 

map_connect -opencl_binary [get_opencl_binary smithwaterman] -src_type "kernel" -src_name "k1" -src_port "M_AXI_GMEM0" -dst_type "core" -dst_name "OCL_REGION_0" -dst_port "M00_AXI"

map_connect -opencl_binary [get_opencl_binary smithwaterman] -src_type "kernel" -src_name "k1" -src_port "M_AXI_GMEM1"  -dst_type "core" -dst_name "OCL_REGION_0" -dst_port "M01_AXI"

map_connect -opencl_binary [get_opencl_binary smithwaterman] -src_type "kernel" -src_name "k1" -src_port "M_AXI_GMEM2" -dst_type "core" -dst_name "OCL_REGION_0" -dst_port "M00_AXI"

Any tips?

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kennetho
Xilinx Employee
Xilinx Employee
20,519 Views
Registered: ‎02-23-2016

Working in 2016.1 HEAD

View solution in original post

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10 Replies
ywu
Xilinx Employee
Xilinx Employee
11,699 Views
Registered: ‎11-28-2007

Ken,

 

What you have looks correct to me. Can you share your design so that I can take a look? Which version of the tool are you using? If you are using 2015.4, I will need to provide you a patch for using C/C++ kernels on 2DDR DSA.

 

 

Cheers,
Jim
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kennetho
Xilinx Employee
Xilinx Employee
11,692 Views
Registered: ‎02-23-2016

Hi Jim,

 

Code is attached. I'm building this with 2016.1 daily branch as the underlying HLS in 2015.4 has a bug exposed by this code.

 

Thanks,

 

Ken

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ywu
Xilinx Employee
Xilinx Employee
11,685 Views
Registered: ‎11-28-2007

Hi Ken,

 

Since this design can compile in 2015.4, so there is nothing wrong as far as usage is concerned. Please file a CR against 2016.1 on this.

 

What issue is exposed by this code in 2015.4? Is there a CR? We did find an issue and a patch is available.

 


@kennetho wrote:

Hi Jim,

 

Code is attached. I'm building this with 2016.1 daily branch as the underlying HLS in 2015.4 has a bug exposed by this code.

 

Thanks,

 

Ken


 

Cheers,
Jim
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kennetho
Xilinx Employee
Xilinx Employee
11,682 Views
Registered: ‎02-23-2016

Hi Jim,

 

I'll file a CR against 2016.1. In 2015.4, we find that HLS increasingly allocates memory until it is killed by the OS. Our build machine has 64GB of ram. I had throught that we had a CR on this, but I am mistaken. Filing now.

 

Best Regards,

 

Ken

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ywu
Xilinx Employee
Xilinx Employee
11,679 Views
Registered: ‎11-28-2007

Hi Ken,

 

Since 2016.1 is already working for this design as far as HLS is concerned, you don't need to file a CR against 2015.4 on the memory issue.


@kennetho wrote:

Hi Jim,

 

I'll file a CR against 2016.1. In 2015.4, we find that HLS increasingly allocates memory until it is killed by the OS. Our build machine has 64GB of ram. I had throught that we had a CR on this, but I am mistaken. Filing now.

 

Best Regards,

 

Ken


 

Cheers,
Jim
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kennetho
Xilinx Employee
Xilinx Employee
11,675 Views
Registered: ‎02-23-2016

Hi Jim,

 

Thanks. I've filed a CR (941250) on the 2016.1 branch.

 

Best Regards,

 

Ken

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ywu
Xilinx Employee
Xilinx Employee
11,669 Views
Registered: ‎11-28-2007

Hi Ken,

 

If you need to try this soon, I will send you a workaround. Otherwise, just wait for the issue to be fixed in 2016.1 branch.

 

 


@kennetho wrote:

Hi Jim,

 

Thanks. I've filed a CR (941250) on the 2016.1 branch.

 

Best Regards,

 

Ken


 

Cheers,
Jim
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kennetho
Xilinx Employee
Xilinx Employee
11,667 Views
Registered: ‎02-23-2016

Hi Jim,

 

A workaround would be greatly appreciated. We're trying to wrap up this project and this is likely our final build.

 

Best Regards,

 

Ken

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ywu
Xilinx Employee
Xilinx Employee
11,664 Views
Registered: ‎11-28-2007

Hi Ken,

 

I will send you the workaround via email.

 


@kennetho wrote:

Hi Jim,

 

A workaround would be greatly appreciated. We're trying to wrap up this project and this is likely our final build.

 

Best Regards,

 

Ken


 

Cheers,
Jim
kennetho
Xilinx Employee
Xilinx Employee
20,520 Views
Registered: ‎02-23-2016

Working in 2016.1 HEAD

View solution in original post

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