08-16-2019 09:24 AM
Hello,
I have to make a design decision for my project and would appreciate input from the community. I have a complex body of C++ code and I would like to offload part of it to an Alveo U280-ES1. The part I am offloading is memory-intensive.
I see two options:
1) Create a MicroBlaze design and use Petalinux, so that I can boot Linux in the FPGA. Once this is in place, then I can just compile the C++ application in the MicroBlaze (I am asssuming it is easy, please correct me if I am wrong). I would only need to define some communication protocol between the host and the FPGA.
2) Use SDAccel. I would have to isolate the parts of my C++ code that I want to offload and adapt them to SDAccel/OpenCL. There isn't a single function that will be offloaded, but rather several functions that communicate with one another, scattered around several files and classes (with inheritance). They use the C++ standard library (I'm not sure if this is a problem).
Since option 1 looks much easier to implement, that is what I initially started working on. However, I am afraid it could be much slower.
This is my first experience with FPGAs, so please treat me as newbie ;).
Thanks
08-18-2019 07:18 PM
The core question is when we should use hardware acceleration (SDAccel)
You can estimate the below question first:
1. Does the Algorithm allow for parallelization?
2. Is the Algorithm compute-intensive?
3. Are there many similar tasks?
If the answers are positive, you can consider SDAccel to accelerate your design.
For the detailed information, please refer to UG1023.