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Visitor
Visitor
235 Views
Registered: ‎11-07-2020

SLR Utilization

I am trying to implement my application on AlveoU200 using SDAccel (2019.1)

 

When I tried hardware emulation for my application, I got 68% for BRAM Utilization and 205% for BRAM Utilization SLR. In this case, I could not run this program because the BRAM capacity in AlveoU200 is not enough. (I got an error that says BRAM capacity is not enough)

On the other hand, I tried another similar application which was 62% for BRAM Utilization and 187% for BRAM Utilization SLR. Even though the BRAM Utilization SLR is over 100%, I could run this program on AlveoU200.

 

I think BRAM Utilization SLR should be less than 100% in order to run on AlveoU200.

Could you tell me why I could run this program?

 

I did not do any SLR assignment manually. 

Does the SDAccel do SLR assignment automatically?

 

 

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Moderator
Moderator
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Registered: ‎11-04-2010

Theoretically, if the BRAM utilization in SLR is more than 100%, the placer for platform link will fail.

You can open the routed dcp and run "report_utilization -slr" to export the actual SLR utilization.

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Visitor
Visitor
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Registered: ‎11-07-2020

Sorry, I don't understand what you mean by opening the routed dcp.

dcp is a directory which will be made after the execution?

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Moderator
Moderator
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Registered: ‎11-04-2010

Vitis will call Vivado in the background.

If you set -R option in Vitis link stage, more intermediate information will be retained. Among them the Design checkpoint file(DCP) will be saved by Vivado. With the dcp after Vivado route_design stage, you can get all the place & route info of the whole design.

(The XX.dcp files are saved in link dir: .../Hardware/binary_container_1.build/link/vivado/vpl//prj/prj.runs/impl_1)  

In Vivado, to open dcp file: File -> Checkpoint -> Open.

You can also Launch Vivado from Vitis after HW flow. (Xilinx -> Vivado Integration -> Open Vivado Project) and open report_utilization command in Vivado TCL Console.

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