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xil_tour
Explorer
Explorer
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Registered: ‎06-14-2018

Simultaneous r/w on multiple memory banks

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Hi,

with 4 DDR banks, is it possible to have like 2 reads and 2 write at the same time ?

The kernel global bandwidth example shows only 1 read and 1 write at a time.

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xil_tour
Explorer
Explorer
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Registered: ‎06-14-2018

I managed to use the 4 banks at the same time, but not with the kernel global bandwidth example, which may have a problem.

 

extern "C" {

void sobel(uint512_dt *inimg, uint512_dt *outimg, uint512_dt *inimg2, uint512_dt *outimg2) {

#pragma HLS INTERFACE m_axi port=inimg  offset=slave bundle=gmem0
#pragma HLS INTERFACE m_axi port=outimg  offset=slave bundle=gmem1
#pragma HLS INTERFACE m_axi port=inimg2  offset=slave bundle=gmem2
#pragma HLS INTERFACE m_axi port=outimg2  offset=slave bundle=gmem3
#pragma HLS INTERFACE s_axilite port=inimg  bundle=control
#pragma HLS INTERFACE s_axilite port=outimg bundle=control
#pragma HLS INTERFACE s_axilite port=inimg2  bundle=control
#pragma HLS INTERFACE s_axilite port=outimg2 bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control

	uint512_dt local_buffer;
	uint512_dt local_buffer2;

	loop_read: for(int line = 0; line < 64*64;  line++) {
#pragma HLS PIPELINE

		local_buffer = inimg[line];
		outimg[line] = local_buffer;
		local_buffer2 = inimg2[line];
		outimg2[line] = local_buffer2;
	}

	return;
	}
}

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Screenshot from 2019-04-04 15-54-55.png
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10 Replies
hongh
Moderator
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1,119 Views
Registered: ‎11-04-2010

All these DDR banks can be used independently.

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xil_tour
Explorer
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1,112 Views
Registered: ‎06-14-2018

How can I achieve that modifying the example ?

#define NDDR_BANKS 4

kernel __attribute__ ((reqd_work_group_size(1,1,1)))
void bandwidth(__global uint16  * __restrict input0,
               __global uint16  * __restrict output0,
               __global uint16  * __restrict input1,
               __global uint16  * __restrict output1,

               ulong num_blocks)
{
    __attribute__((xcl_pipeline_loop))
    for (ulong blockindex = 0; blockindex < num_blocks; blockindex++) {
        uint16 temp0 = input0[blockindex];
        output0[blockindex] = temp0;
        uint16 temp1 = input1[blockindex];
        output1[blockindex] = temp1;

    }
}

It should already be 2 read + 2 write at the same time, but for some reason, it's not the case.

Screenshot from 2019-03-28 17-26-43.png
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bchebrol
Xilinx Employee
Xilinx Employee
1,078 Views
Registered: ‎06-04-2018

Is the DDR mapping changed in config.mk file?

Add the appropriate changes for LDCLFLAGS in config.mk file

Regards,
Vishnu
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xil_tour
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Registered: ‎06-14-2018

I see no config.mk file in the project folder.

Can you explain "appropriate changes" please ?

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bchebrol
Xilinx Employee
Xilinx Employee
1,058 Views
Registered: ‎06-04-2018

Hi @xil_tour,

you can find config.mk file in the following path : 

https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/kernel_to_gmem/kernel_global_bandwidth

Based on number of banks you want to use, you can set ddr_banks variable and corresponding banks.

Regards,
Vishnu
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xil_tour
Explorer
Explorer
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Registered: ‎06-14-2018

Can't I change that after having imported the project in SDx ?

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bchebrol
Xilinx Employee
Xilinx Employee
1,034 Views
Registered: ‎06-04-2018

Hi @xil_tour,

Under the Hardware Functions, right click the kernel and select "Edit XOCC Options",

if you are using 1DDR then add    :  --sp bandwidth_1.m_axi_gmem0:DDR[0]

if you are using 2DDR then add  : --sp bandwidth_1.m_axi_gmem0:DDR[0] --sp bandwidth_1.m_axi_gmem0:DDR[1]

According based on number of DDR's you can add to XOCC Options.

Regards,
Vishnu
----------------------------------------------------------------------------------------------
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xil_tour
Explorer
Explorer
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Registered: ‎06-14-2018

I already have this in the "XOCC Options" :

 

--sp bandwidth_1.m_axi_gmem0:bank0 --sp bandwidth_1.m_axi_gmem1:bank1 --sp bandwidth_1.m_axi_gmem2:bank2 --sp bandwidth_1.m_axi_gmem3:bank3

Are DDR[0] and bank0 valid aliases ?

 

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bchebrol
Xilinx Employee
Xilinx Employee
992 Views
Registered: ‎06-04-2018

Hi @xil_tour,

yes, DDR[0] and bank0 are valid aliases.

Regards,
Vishnu
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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----------------------------------------------------------------------------------------------

xil_tour
Explorer
Explorer
984 Views
Registered: ‎06-14-2018

I managed to use the 4 banks at the same time, but not with the kernel global bandwidth example, which may have a problem.

 

extern "C" {

void sobel(uint512_dt *inimg, uint512_dt *outimg, uint512_dt *inimg2, uint512_dt *outimg2) {

#pragma HLS INTERFACE m_axi port=inimg  offset=slave bundle=gmem0
#pragma HLS INTERFACE m_axi port=outimg  offset=slave bundle=gmem1
#pragma HLS INTERFACE m_axi port=inimg2  offset=slave bundle=gmem2
#pragma HLS INTERFACE m_axi port=outimg2  offset=slave bundle=gmem3
#pragma HLS INTERFACE s_axilite port=inimg  bundle=control
#pragma HLS INTERFACE s_axilite port=outimg bundle=control
#pragma HLS INTERFACE s_axilite port=inimg2  bundle=control
#pragma HLS INTERFACE s_axilite port=outimg2 bundle=control
#pragma HLS INTERFACE s_axilite port=return bundle=control

	uint512_dt local_buffer;
	uint512_dt local_buffer2;

	loop_read: for(int line = 0; line < 64*64;  line++) {
#pragma HLS PIPELINE

		local_buffer = inimg[line];
		outimg[line] = local_buffer;
		local_buffer2 = inimg2[line];
		outimg2[line] = local_buffer2;
	}

	return;
	}
}

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Screenshot from 2019-04-04 15-54-55.png
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