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Participant
Participant
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Registered: ‎06-15-2020

Super Long Lines (SLLs) capacity is violated error

Hello!

I am using Vitis accel with the AWS platform (target device is xcvu9p-flgb2104-2-i if I remember correctly). I am doing sparse matrix-vector multiplication in my project. Every row in the matrix has the same number (40) of non-zero entries. In the SpMV implementation, I complete parallelized operations on these 40 non-zero entries in the vector dot product within matrix-vector multiplication.

The size of the matrix is (500x500) so the actual size is 500x40 in this case. During hardware emulation, the report shows the following resource usage:

BRAM591%
DSP2874%
FF1595436%
LUT27454923%

 

Then in hardware build, I encountered this error message (using all default compilation settings):

Phase 2 Global Placement

Phase 2.1 Floorplanning
ERROR: [Place 30-864] Super Long Lines (SLLs) capacity is violated between Super Logic Regions (SLR): 1 and SLR: 2 for PBlock: pblock_SH. SLLs required = 5309, SLLs available = 0.
ERROR: [Place 30-864] Super Long Lines (SLLs) capacity is violated between Super Logic Regions (SLR): 0 and SLR: 1 for PBlock: pblock_CL. SLLs required = 32436, SLLs available = 11520.
ERROR: [Place 30-864] Super Long Lines (SLLs) capacity is violated between Super Logic Regions (SLR): 1 and SLR: 2 for PBlock: pblock_CL. SLLs required = 32436, SLLs available = 11520.
Phase 2.1 Floorplanning | Checksum: b6dc6407

 

I understand the non-constant array access pattern built in the algorithm needs large muxes (which could be a reason), but I am wondering if there exist other possible workarounds (compilation settings/resource specifications etc.) for this issue. Please let me know if you would like me to provide more details. Thank you!!

 

Owenoool

1 Reply
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Moderator
Moderator
151 Views
Registered: ‎11-04-2010

It's the Vivado placer issue during the VPL. Please provide opt.dcp of the design and ask help in Implementation board.

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