Vitis 2020.1 XFSBL file generation failed

[arashr]

Hi,

I have updated from Vivado/SDK 2019.1 to version 2020.1. I have created a platform with "boot generation" on to have FSBL. When I try building platform project, I get an error saying FSBL cannot be compiled. The problem is what is described here.  I tried compiling it through terminal and I got this output:

aarch64-none-elf-gcc -o executable.elf  xfsbl_authentication.o  xfsbl_misc.o  xfsbl_sd.o  xfsbl_csu_dma.o  xfsbl_plpartition_valid.o  xfsbl_board.o  xfsbl_image_header.o  psu_init.o  xfsbl_handoff.o  xfsbl_initialization.o  xfsbl_dfu_util.o  xfsbl_main.o  xfsbl_hooks.o  xfsbl_misc_drivers.o  xfsbl_usb.o  xfsbl_bs.o  xfsbl_nand.o  xfsbl_rsa_sha.o  xfsbl_qspi.o  xfsbl_ddr_init.o  xfsbl_partition_load.o  xfsbl_exit.o  xfsbl_translation_table.o  -MMD -MP      -Wall -fmessage-length=0 -DARMA53_64 -Os -flto -ffat-lto-objects    -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilsecure,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilpm,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-lmetal,-lgcc,-lc,--end-group                                                                                                           -Wl,--start-group,-lxil,-lgcc,-lc,-lmetal,--end-group -n  -Wl,--gc-sections -Lzynqmp_fsbl_bsp/psu_cortexa53_0/lib -Tlscript.ld
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: executable.elf section `.stack' will not fit in region `psu_ocm_ram_0_S_AXI_BASEADDR'
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffebf60 of executable.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffebf60 of executable.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: address 0xfffebf60 of executable.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: section .handoff_params VMA [00000000fffe9e00,00000000fffe9e87] overlaps section .stack VMA [00000000fffe8440,00000000fffea43f]
/tools/Xilinx/Vitis/2020.1/gnu/aarch64/lin/aarch64-none/x86_64-oesdk-linux/usr/bin/aarch64-xilinx-elf/aarch64-xilinx-elf-ld.real: region `psu_ocm_ram_0_S_AXI_BASEADDR' overflowed by 8800 bytes
collect2.real: error: ld returned 1 exit status
Makefile:29: recipe for target 'executable.elf' failed
make: *** [executable.elf] Error 1

I couldn't find related questions in the forums for these issues. What is happening and what is causeing this problem?

Thank you

[arashr · Accepted solution]

Wow, found the solution completely by random.

If you've got this issue, open all BSP settings (or domains?) you have and click on "Modify BSP Settings..."

And then click on standalone and then change zynqmp_fsbl_bsp to true.

It seems to activate optimization for FSBL. I really don't know why it fixed it. I hope somebody who knows what happened can comment on that and also comment on how to "properly" fix the problem without turning on the optimization. 

Thank you

[joe306]

Your a genius sent to help people like me.

I have the same problem but I am using Vivado/Vitis 19.2.

Will give it a try

Thank you

[joe306]

I get this message after I update my Vivado design and in Vitis I run the tool Update Hardware Specification. To get around the error I had to delete the Platform and create it again. Will let you know if your work around solves this error. Thank you

[LearningXilinx]

Thanks, did this (just for the FSBL) and it worked.

I believe what happened is turning on the optimizations makes the code smaller, so the .elf now fits in that memory region.

However, the more correct approach is to modify the linker script to the correct size...but since I don't have a complete understanding of the memory map and am running the evaluation, will just use this solution for now. Also, what made the image larger or is something else taking up space in that region ?

[arashr]

@LearningXilinx I'm glad it worked for you.
Your comment makes sense. Though to this date, I have been doing this very exact same thing every time I updated the hardware description file because updating the design file reverts optimization back to false and the error appears again.

[joe306]

Thank you very much for find a solution. I don't have the understanding for linker script either.

[joe306]

Thank you.

[LearningXilinx]

Looks like it is contained to this region:

region `psu_ocm_ram_0_S_AXI_BASEADDR' overflowed by 8800 bytes

If this section can be increased, that might solve it but would have to play around with it if time permits...

[arashr]

Ok, Thank you for the clue! I'll try to track it down. This is actually an interesting issue.

[arashr]

@LearningXilinxThis problem is fixed in Vivado 2020.2. I upgraded to the latest version (2020.2) and I don't need to change the optimization parameter every time I update the hardware description.

[joe306]

Hello and thank you for letting us know.

Happy New Years!