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Adventurer
Adventurer
820 Views
Registered: ‎09-17-2018

Vitis builds BOOT.BIN without bitstream

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Hello, I have a problem with programing PL with Vitis using hardware accelerated flow. I have generated project and petalinux according to Adam Taylor guide zyng7000 but while generating boot.bin console says:

Generating bif file for the system project
Executing command '::scw::generate_bif -xpfm /home/bartek/workspace/platformqspi/export/platformqspi/platformqspi.xpfm -domains linux_domain -bifpath /home/bartek/workspace/Caramelldansen_system/Debug/system.bif' on XSCT
sdcard_gen --xpfm /home/bartek/workspace/platformqspi/export/platformqspi/platformqspi.xpfm --sys_config platformqspi --bif /home/bartek/workspace/Caramelldansen_system/Debug/system.bif --no_bitstream --sd_file /home/bartek/workspace/Caramelldansen/Hardware/Caramelldansen.exe
Running /tools/Xilinx/Vitis/2019.2/bin/bootgen  -image /home/bartek/workspace/Caramelldansen_system/Debug/sd_card_temp/boot.bif -w -o i BOOT.BIN

I saw --no_bitstream option which is weird so I tried to use my platform bitstream manually but then system hangs up while configuring kernel.

This is bif that I'm using:

//arch = zynq; split = false; format = BIN
the_ROM_image:
{
[bootloader] <zynq_fsbl.elf>
<bitstream>
<u-boot.elf>
}

//rootfs is extracted on /dev/mmcblk1p2
//image.us is on /dev/mmcblk1p1

Bitstream should be initialized by zynq_fsbl.elf in boot.bin, but <bitstream> option doesn't include bitstream.in boot.bin

If I manually package boot.bin with bitstream from platform, system normally boots but it  frezzes while programming CL_device[0]: edge (something like that)

What could be wrong? Why Vitis isn't generating new bitstream and is not including it in boot.bin?

Thanks.

PS. I don't know if it is important but I'm using qspi as boot mode for my board.

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Adventurer
Adventurer
704 Views
Registered: ‎09-17-2018

The problem was because I have loaded bitstream from older implemenation of this project to BOOT.BIN. Vitis had old bitstream in hardware folder, so I have opened Xilinx>Vivado Integration>Open Project, generated new bitstream because it said that synthesis and implementation is out-of date manually exported new bit and included it in BOOT.BIN.

Wrong programing xclbin or wrong bitstream would cause infinite programming loop in my device (programming CL_device[0]: edge).

I have manually created platform for Minized from scratch and build system for it. I have created petalinux that takes fsbl+fpga+uboot (BOOT.BIN) from QSPI and then reads image.ub from emmc partition1 and rootfs from emmc partition2.

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Adventurer
Adventurer
769 Views
Registered: ‎09-17-2018

Okay, so I find out that opening vivado integrator and manually generating, exporting bitstream then merging it with boot.bin works.

I think that I have some linking problem or something.

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Moderator
Moderator
719 Views
Registered: ‎09-12-2007

The linux will crash if the PL is not configured and you have IP drivers in the PL probing. However ,looks like you resolved this by manually updating the bif, and calling bootgen.

 

For your other issue:

while programming CL_device[0]: edge (something like that)

What platform are you using?

Adventurer
Adventurer
705 Views
Registered: ‎09-17-2018

The problem was because I have loaded bitstream from older implemenation of this project to BOOT.BIN. Vitis had old bitstream in hardware folder, so I have opened Xilinx>Vivado Integration>Open Project, generated new bitstream because it said that synthesis and implementation is out-of date manually exported new bit and included it in BOOT.BIN.

Wrong programing xclbin or wrong bitstream would cause infinite programming loop in my device (programming CL_device[0]: edge).

I have manually created platform for Minized from scratch and build system for it. I have created petalinux that takes fsbl+fpga+uboot (BOOT.BIN) from QSPI and then reads image.ub from emmc partition1 and rootfs from emmc partition2.

View solution in original post

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