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Observer
Observer
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Registered: ‎09-11-2019

Why are both m_axi and s_axilite used here to declare the same port ?

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It's in the page 549 of the UG1393. I don't understand why both m_axi and s_axilite are used to declare the same port like matA. Why doesn't it use just m_axi ?

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Advisor
Advisor
229 Views
Registered: ‎04-26-2015

This approach creates an AXI Master for transferring data, with the address offset of the AXI Master set via AXI Lite (Slave). It's a common design and works very well.

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Advisor
Advisor
230 Views
Registered: ‎04-26-2015

This approach creates an AXI Master for transferring data, with the address offset of the AXI Master set via AXI Lite (Slave). It's a common design and works very well.

View solution in original post

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Observer
Observer
134 Views
Registered: ‎09-11-2019

I got it ! Thank you for your reply !

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