01-11-2021 03:32 PM
I'm new with vitis and acceleration on FPGA. I built a module to accelerate, and it passes the c-simulation, and the co-simulation. After the co-simulation, in the summary there is the min/avarage/max latency in ns taken by the module in order to complete the execution. However, when i run the module on the board, the execution time is much larger than the one estimated by vitis. In particular, vitis estimate the execution time in 2ms, while on the board the execution time is 15ms. How it can be possible?
01-11-2021 07:44 PM
Can I ask, how did you build your platform package in Vitis? Did you build your own block design and export it as a Platform Interface?
Also, does the execution time represent the time taken for data transfer as well? From what I understand, Vitis accelerated logic comprises of a data transfer to global memory which is then used by the hardware logic. Is this transfer time taken into account when calculating the 2 ms execution time?
01-12-2021 01:54 AM
Hi @prateekmohan1 ,
Yes, i created the platform by downloading a script that created a custom block design using vivado. Then i created a new platform project with vitis using the .xsa file created before. As far as i know, the execution time should include also the time taken for data transfer. However, i think this type of calculation is optimistic. In fact, i think that the problem could be the fact that i read byte per byte the data from the memory instead of reading the whole word lenght, but i'm not shure about this. Any ideas?
01-12-2021 07:28 PM
Can you share what script you used to create that custom block and what your source code for acceleration is doing? Perhaps from there I can understand further as to why this is slow.
Also, you mention reading byte per byte - where is the memory you are reading from? Is it from DDR?