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kemache
Observer
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Registered: ‎05-07-2018

fixed size array

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Hello,

 

I would like to declare an array with fixed size elements (7 bits) in SDSoC. For that there are 2 libraries for HLS (ap_cint.h for C and ap_int.h for C++). For example:

 

main.cpp

 

#include <iostream>
#include <stdlib.h>
#include <stdint.h>
#include "ap_int.h"
#include "test.h"
#include "sds_lib.h"

 

int main(int argc, char* argv[]){
ap_uint<7> var[2];
//var = (ap_uint<7> *)sds_alloc(2*sizeof(ap_uint<7>));
test(var);
printf("TEST \n");
return 0;
}

 

test.cpp

 

#include "ap_int.h"
#include "test.h"


void test (ap_uint<4> var[2]){
//#pragma HLS ARRAY_PARTITION variable=var dim=0 complete // The pragma ensures that it's a bunch of registers rather than RAM-style addressing
//for (int i=0; i<4; i++)
//#pragma HLS PIPELINE
var[0]=2;
var[1]=4;

}

 

In C I encountered  the following error just by including the library:

 

SdsCompiler 83-5019: Exiting sdscc : Error when calling 'arm-linux-gnueabihf-gcc -c -I../src -Wall -O3 -fmessage-length=0 -MMD -MP -D __SDSCC__ -MT/users/cao/kemache/workspace/test_naif/Release/src/main.o -MF/users/cao/kemache/workspace/test_naif/Release/src/main.d -MT/users/cao/kemache/workspace/test_naif/Release/src/main.o -I /users/soft/xilinx/2018.2/SDx/2018.2/target/aarch32-linux/include -D HLS_NO_XIL_FPO_LIB -I /users/soft/xilinx/2018.2/Vivado/2018.2/include /users/cao/kemache/workspace/test_naif/src/main.c -o src/main.o'

 

In C++ the declation is as follow: ap_uint<7> var[2] with that I get the following error:

 

BRAM data width (2-bits)/(7-bits) for port ‘var_V_PORTA’ must be a multile of 8
You can use a Vivado HLS interface pragma to an AXI4 stream interface.

 

And when I try to use a multiple of 8 like 24 or 40 I get the following error:

 

Argument number 1 of caller in main.cpp at line 13 has data size of 8/16 bytes while callee data size is 6/10 bytes 

 

So, please how can I declare it correctly in SDSoC ?

 

 

 

 

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kemache
Observer
Observer
846 Views
Registered: ‎05-07-2018

Hello,

 

For C++ project, I found the solution of that the size have to be multiple of 8 or the difference between the size of the variable in the main and in the hardware function. And I would like to share it with you in case where someone have to deal with the same problems.

 

I had to use the axi stream interconnect by using the following pragma just before the hardware function :

 

#pragma SDS data copy(var[0:SIZE])
#pragma SDS data access_pattern(var:SEQUENTIAL)

 

void test (ap_uint<7> var[SIZE]){

 

// hardware function instructions

.

.

}

 

Thank you,

 

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kemache
Observer
Observer
847 Views
Registered: ‎05-07-2018

Hello,

 

For C++ project, I found the solution of that the size have to be multiple of 8 or the difference between the size of the variable in the main and in the hardware function. And I would like to share it with you in case where someone have to deal with the same problems.

 

I had to use the axi stream interconnect by using the following pragma just before the hardware function :

 

#pragma SDS data copy(var[0:SIZE])
#pragma SDS data access_pattern(var:SEQUENTIAL)

 

void test (ap_uint<7> var[SIZE]){

 

// hardware function instructions

.

.

}

 

Thank you,

 

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