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Visitor
Visitor
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Registered: ‎10-13-2020

vitis problem

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I have package a processor kernel into a vitis development. when i load a program to processor. I got this result. Some are rigtht, and others are wrong.  I want to know whether is vitis development problem or my processor have something wrong.

a.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-11-2011

Is the "failed" message coming from your host/application code? I would suggest running your design via the debugger so you can step through your code and make sure that the values you are calculating are the ones you are expecting.

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Xilinx Employee
Xilinx Employee
100 Views
Registered: ‎01-11-2011

Is the "failed" message coming from your host/application code? I would suggest running your design via the debugger so you can step through your code and make sure that the values you are calculating are the ones you are expecting.

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Visitor
Visitor
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Registered: ‎10-13-2020

thanks! My design has problem. I have sloved it.

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