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Visitor
Visitor
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Registered: ‎06-16-2019

SDAccel Compilation Order

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Hello everyone,

I am new with FPGAs, SDAccel (Version 2018.2) and OpenCL. I am trying to run Vector addition example on FPGA ZCU102. But I am stuck at compilation part.

I tried the following steps. ('hello' is the project name)

1. Software Emulation : Build and then run hello.exe (Got TEST PASSED on Console)

2. Hardware Emulation : Build and then run binary_container_1.xclbin (Got TEST PASSED on console)

3.System : Build for hardware target ( I got bitstream file after this : zcu102_wrapper.bit)

I have following doubts.

1. Is this order correct?

2. What to do next? (In order to implement it on FPGA)

3. What is exactly happening in each step? (If we compare it to Vivado)

Please help me with these doubts ASAP.

Thanks

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-04-2018

Re: SDAccel Compilation Order

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Hi @new_bee,

1. Yes, the order is correct.

2. You need to run on FPGA using the bit stream file to check the correctness on board(ZCU102).

3. To explain about what is happening in each step : 

     a. sw_emu :  This step ensures the functional correctness. (Takes couple of minutes to complete)

     b. hw_emu  : This step check the correctness of the logic generated for the custom compute units. ( Time taken to complete this step is slightly more compared to sw_emu)

     c. hw  : After the above two(sw_emu and hw_emu) are passing we will run on board to check the expected throughput and other results (This takes couple to hours to finish).

As the process of generating the bitstream is time consuming(multiple hours), we test the fuctional and logical correctness using sw_emu/hw_emu and then we go for hw.

Regards,
Vishnu
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Xilinx Employee
Xilinx Employee
267 Views
Registered: ‎06-04-2018

Re: SDAccel Compilation Order

Jump to solution

Hi @new_bee,

1. Yes, the order is correct.

2. You need to run on FPGA using the bit stream file to check the correctness on board(ZCU102).

3. To explain about what is happening in each step : 

     a. sw_emu :  This step ensures the functional correctness. (Takes couple of minutes to complete)

     b. hw_emu  : This step check the correctness of the logic generated for the custom compute units. ( Time taken to complete this step is slightly more compared to sw_emu)

     c. hw  : After the above two(sw_emu and hw_emu) are passing we will run on board to check the expected throughput and other results (This takes couple to hours to finish).

As the process of generating the bitstream is time consuming(multiple hours), we test the fuctional and logical correctness using sw_emu/hw_emu and then we go for hw.

Regards,
Vishnu
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post