01-02-2019 07:28 AM
I have an included RTL module in my blockdesign using the following menu:
My module has several AXI-STREAM interface:
These stream interfaces uses the same clock and reset (M_AXIS_ACLK) (The AXI-Lite interface has separate dedicated clock and reset)
The module works properly, but I always get a warning that no associated clock found for these stream interfaces.
I get this warning even if I set the Clock domain for each stream interface by double clicking on them.
How can I eliminate these warnings?
Is there any HDL atttribute, or constraint, or naming convention, or should I implement as many clock ports as stream interface.
01-02-2019 07:36 AM
Your picture is very zoomed in... Are you saying you have attached both master and 'slave' clocks, and still get the warning?
If suspect the slave is not connected. (If you didn't use the slave, that master may still be functional.)
If so, please mark as solution accepted (and Kudos accepted).
01-02-2019 11:32 AM
As I mentioned the IP works properly, (all interfaces are connected properly)
Note, that I get warning only for the four SLAVE AXI-STREAM interface. (The Lite interface has a separate, dedicated clock, which is found by the tool) And the MASTER STREAM interface also found the clock, because the naming convention.
But I use the same clock on the master and slave stream ports (this module doesnt do a clock convertion) and therefore, the slave interfaces cannot find the clock by default based on the names.
My question is that is there any way to say to Vivado which interface uses which clock. To eliminate warnings.
01-02-2019 11:45 AM
If I understand you now... You know the design is good and you just want to silence the warning message...
YES... You can use the set_msg_config command