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Visitor
Visitor
14,242 Views
Registered: ‎03-08-2014

Block memory generator v8.2, Vivado 2014.1, stand alone mode, port width

Hi,

 

In Vivado 2014.1 I have problems with configuration of the Block Memory Generator (8.2). When recustomizing the IP I select Stand Alone on the Basic tab. Then on the Port A Options I'm not able to change the port width and depth values.

 

This did work in Vivado 2013.4. When upgrading a project from 2013.4 to 2014.1 containing a BMG IP, the values for port width and depth are maintained (in my case different from the default) but not changeable.

 

--

H

 

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8 Replies
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Moderator
Moderator
14,236 Views
Registered: ‎01-16-2013

Hello @hiwe ,

 

I am able to change the values in Vivado 2014.1.

Please refer below snapshot. 

IP.PNG

 

First click on cross and then edit the value for write width and write depth.

Use drop down options for Read width.

 

 

Thanks,

Yash

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Xilinx Employee
Xilinx Employee
14,228 Views
Registered: ‎02-06-2013

Hi

 

When used in Block design only Mode and memory options available.

All other parameters are set during validation of the design through parameter propagation.

 

You can change width and depth parameters only when used through Vivado IP Catalog.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
14,224 Views
Registered: ‎08-01-2008

You  need to change value in Address editor

Thanks and Regards
Balkrishan
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Moderator
Moderator
14,188 Views
Registered: ‎01-16-2013

Hello @hiwe,

 

Did your issue resolved?

If yes, please mark the post as accepted solution which was helpful and close the thread.

Your small effort to close the thread by accepting the answer will help us to moderate the forum and provide better assistance.

 

Thanks,

Yash

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Visitor
Visitor
14,158 Views
Registered: ‎03-08-2014

Hi Satish,

 

Sorry for late reply. Your answer put me in the right direction, I've at least managed to get it work. These are basically the steps I followed.

 

1. Open a Managed IP project and customize the the block memory generator. In this context I can, as you said, customize all aspects of the IP. In a block design context the options are far less.

 

2. Generate output products.

 

3. Package the synth directory (containing the vhd-file of the customized IP). This will produce a zip-file packaged IP that I put into some IP repository.

 

4. In the application project, add the IP repository directory.

 

5. Finally add the IP to the block design.

 

Thanks,

--

H

 

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Visitor
Visitor
13,922 Views
Registered: ‎01-21-2014

Hi hiwe, I'd like to see those steps work for me, but in your steps 2 and 3 when I generate output products I don't get any design files like the vhd-file in the synth directory. Am I missing a setting that will produce this?

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Adventurer
Adventurer
13,591 Views
Registered: ‎06-25-2014

I can set the size with BMG 8.1 in 2013.4. But can't set it with BMG 8.2 in 2014.2. What may be the problem?

 

Thanks.

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Participant
Participant
9,128 Views
Registered: ‎07-08-2013

After you make the change in the address editor, to set the memory to say 64k, and then go back to the block diagram viewer, the value in the blk_mem_gen ip is still the greyed out default {8192}.  So you are saying we should just ignore this?

 

I am using 2015.3 and this still happens - you appear to be able to specify the write depth in the IP configurator, but the value is fixed and greyed out; changing it in the address editor appears to work; but doesn't change the greyed out value.

 

 

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