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Scholar dwisehart
Scholar
11,891 Views
Registered: ‎06-23-2013

Cannot add ILA probes

When I have ILA turned off, my fairly small test shows positive WNS the first time WNS is listed and not too many resources are consumed:

 

2014-06-13_17-00-21_01.png

 

 

When I try to implement the design with two ILA probes enabled, the implementation fails with the error:

 

ERROR: [Place 30-149] Unroutable Placement! A MMCM / (BUFIO/BUFR) component pair is not placed in a routable site pair. The MMCM component can use the dedicated path between the MMCM and the (BUFIO/BUFR) if both are placed in the same clock region or if they are placed in horizontally adjacent clock regions. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

 

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mFPGA/genTxClk[1].mTxClk/w6466Clk] >

 

mFPGA/genTxClk[1].mTxClk/mMMCM (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y8

 

mFPGA/genTxClk[1].mTxClk/mBuf6466 (BUFR.I) is provisionally placed by clockplacer on BUFR_X1Y29

 

The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances.

 

 

 

All of the clock rules have a status of "pass" and the MMCM that is failing is not associated--at least by me--with the ILA probes.  Your thoughts?  I attached the XDC file for the probes.

 

Thanks,
Daniel

 

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8 Replies
Scholar dwisehart
Scholar
11,882 Views
Registered: ‎06-23-2013

Re: Cannot add ILA probes

Interestingly, I replaced the BUFR with a BUFG, now I have two errors:

 

ERROR: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.


< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mFPGA/genA[1].mC/mGT/gtwizard_10g_6466_i/gt0_gtwizard_10g_6466_i/iClk] >

 

ERROR: [Place 30-139] Unroutable Placement! A GT / MMCM component pair is not placed in a routable site pair. The GT component can use the dedicated path between the GT and the MMCM if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.


< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets mFPGA/genB[5].mC/mGT/gtwizard_10g_6466_i/gt0_gtwizard_10g_6466_i/iClk] >

 

Daniel

 

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Xilinx Employee
Xilinx Employee
11,864 Views
Registered: ‎09-20-2012

Re: Cannot add ILA probes

Hi,

 

Did you try locking the GT and MMCM to same clock region?

 

If possible please share the test case (post synthesis DCP would be sufficient).

 

Thanks,

Deepika.

Thanks,
Deepika.
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Scholar dwisehart
Scholar
11,856 Views
Registered: ‎06-23-2013

Re: Cannot add ILA probes

I did not try locking them down, Deepika.  For the non-probed design I figured that the tools would do a better job of placing the components than I would, so I specify the GT pins but not the MMCM locations.  I will give that a try on Monday.  I have attached the DCP file.

 

Regards,

Daniel

 

 

 

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Xilinx Employee
Xilinx Employee
11,827 Views
Registered: ‎09-20-2012

Re: Cannot add ILA probes

Hi,

 

I dont see error when running place_design (after opt_design).

 

I dont see any nets with "MARK_DEBUG" set to TRUE in the design. Is this the correct checkpoint?

 

Thanks,

Deepika. 

Thanks,
Deepika.
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Scholar dwisehart
Scholar
11,825 Views
Registered: ‎06-23-2013

Re: Cannot add ILA probes

This is the checkpoint with the Debug.xdc disabled--and it does run opt_design just fine.  It is when Debug.xdc is enabled that opt_design fails.

 

Do you want me to create a DCP with Debug.xdc enabled?

 

Regards,

Daniel

 

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Xilinx Employee
Xilinx Employee
11,824 Views
Registered: ‎09-20-2012

Re: Cannot add ILA probes

Hi,

 

Yes, please attach the checkpoint (post synthesis or post opt_design) where placer fails with GT MMCM error.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Scholar dwisehart
Scholar
11,821 Views
Registered: ‎06-23-2013

Re: Cannot add ILA probes

Here is the with-debug DCP.  The other difference that might make this not what you want is that I have now locked the GTHE2_COMMON, MMCME2_ADV and BUFHCE's into place that were giving me trouble.  If you want me to unlock them, I will create a third DCP.

 

Regards,

Daniel

 

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Scholar dwisehart
Scholar
11,819 Views
Registered: ‎06-23-2013

Re: Cannot add ILA probes

Here is the DCP with nothing locked down (except the GT pins).  It fails with the MMCM placement error.

 

Daniel

 

 

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