[Chipscope 16-213] The debug port 'dbg_hub/clk' has 1 unconnected channels (bits). This will cause errors during implementation.

[krishnachandrasekhar100]

Hi everyone,

I am working with JESD reference design KCU105_AFE74xx_XCVR_2x44210_7p3728G .I get the following error when I try to implement the design after successful synthesis. I referred to some of the forum posts here for the same error but could not find out what to do.

I get this critical warning when I try to validate the block design

Can someone suggest how do I solve this issue? Where I might have went wrong?

Thanks in advance,

-Chandrasekhar DVS

[krishnachandrasekhar100]

Any help is appreciated on this issue.

Awaiting a reply,

-Chandrasekhar DVS