08-10-2009 02:09 AM
I'm trying to run a IBERT on a few of the GTX transceivers on the virtex 5 FX 100 FPGA we have here. We are using chipscope version 11.2 and it always fails during the
Synthesizing step. The error in the log is
* Synthesizing Core (Step 1 of 6) *
Running: xst -intstyle silent -ifn ibert_drp_wrap.xst
Start Time: Fri Aug 07 16:52:00 EST 2009
ERROR:HDLCompilers:26 - "C:\Xilinx\11.1\ChipScope\bin\nt\data\ibert_v5gtx_drp.xz" line 1 expecting 'EOF', found 'XlxV61EB'
ERROR:HDLCompilers:26 - "C:\Xilinx\11.1\ChipScope\bin\nt\data\ibert_v5gtx_drp.xz" line 1 Closing quote missing in string literal
End Time: Fri Aug 07 16:52:01 EST 2009
Step 1 Elapsed Time: 00:00:00
Total Elapsed Time: 00:00:00
* Synthesizing Core Failed *
is this an issue with 11.2 ? This seems like an application error with enabling 4 GTX modules with a line rate of 3.125Gbps shouldn't cause this.
I did revert to 11.1 which doesn't have the same error during creating the .bit file instead when I download the bit file onto our virtex 5 it
prints an error in the console saying ERROR : IBERT core not ready ?
Next I tried 10.1 , and it seems to fail during the mapping design step . This was in the log
* Mapping Design (Step 4 of 6) *
Running: map -intstyle silent -w -ol high -cm speed -o ibert_top.map.ncd ibert_top.ngd
Start Time: Mon Aug 10 18:49:51 EST 2009
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
End Time: Mon Aug 10 18:55:43 EST 2009
Step 4 Elapsed Time: 00:05:52
Total Elapsed Time: 00:12:30
* Mapping Design Failed *
* IBERT Design Generation Failed *
Check ibert.log for errors
Which really doesn't tell me much
Any ideas ?
Any ideas ?
02-24-2010 08:53 PM
In the GPIO settings(BERT Core Generator GUI) if you have checked the Add VIO Controlled output pins
then please make sure that all the pins you add are unique otherwise the Mapping will FAIL.
I had the same issue where inadvertently two VIO's were assigned the same pins.
After correcting this the mapping is fine and core is generated.