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Observer tallman18
Observer
6,689 Views
Registered: ‎05-01-2008

Chipscope <CoreGen>:ERROR:sim:877

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Hi, I am using ISE 13.1 WebPACK. I have a design which implements with no problem. However, when I tried to add a chipscope source inside ISE(or try to use core inserter) and run implementation I have the following error:

 

Loading CDC project D:\sil\ss.cdc
Successfully read project D:\sil\ss.cdc
copy D:\sil\sss_cs.ngc => D:\sil\_ngo\sss_cs_signalbrowser.ngo
Generating cores using CORE Generator.  Please be patient as this can take several minutes...
     Generating core 1 of 2 icon_pro.ngc...
        >Gathering HDL files....
        >Creating XST project...
        >Creating XST script file...
        >Creating XST instantation file...
        >Running XST................................
        >Generating VHDL structural model...
        >Creating ISE instantiation template.......
        >Core generation step complete.
     Generating core 2 of 2 ila_pro_0.ngc...
FAILED.

<CoreGen>:WARNING:coreutil - Failed to generate file: example_design_vhd
<CoreGen>:ERROR:sim - Error found during generation.
<CoreGen>:ERROR:sim - Failed to generate 'ila_pro_0'.  Error found during generation.
<CoreGen>:ERROR:sim:877 - Error found during execution of IP 'ILA (ChipScope Pro -
See CoreGen Log D:\sil\_ngo\cs_ila_pro_0\coregen.log
ERROR:ChipScope: Unable to generate ila_pro_0.ngc
ERROR:ChipScope: Double-click the ss.cdc icon in the sources window to edit and fix the CDC project.

 

The platform is Windows 7 Enterprise 64 bit. This one is my PC at work.

I tried the same thing at home(ISE WebPACK 13.1 + Windows 7 Home 64 bit). It is succesfully implemented.

Any help appreciated.

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1 Solution

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Observer tallman18
Observer
8,085 Views
Registered: ‎05-01-2008

Re: Chipscope <CoreGen>:ERROR:sim:877

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After I have searched forums, Xilinx WebSite and a couple of hours on google, I ended up with no answer or info. Since I am not admin on the PCs at work I tried at home a lot.

That might be the only reason as far as I figured out, if you are not admin on the PC, chipscope gives the mentioned error. I created a user(not admin) on my notebook, opened the same project and run. It gave the same error. However, when I switch the user to admin it succesfully implements.  I saw some poeple also have the same error, hope it will a solution for them.

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4 Replies
Observer tallman18
Observer
8,086 Views
Registered: ‎05-01-2008

Re: Chipscope <CoreGen>:ERROR:sim:877

Jump to solution

After I have searched forums, Xilinx WebSite and a couple of hours on google, I ended up with no answer or info. Since I am not admin on the PCs at work I tried at home a lot.

That might be the only reason as far as I figured out, if you are not admin on the PC, chipscope gives the mentioned error. I created a user(not admin) on my notebook, opened the same project and run. It gave the same error. However, when I switch the user to admin it succesfully implements.  I saw some poeple also have the same error, hope it will a solution for them.

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Teacher rcingham
Teacher
6,654 Views
Registered: ‎09-09-2010

Re: Chipscope <CoreGen>:ERROR:sim:877

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Tools that require Admin privilege to run is definitely a bug!

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Xilinx Employee
Xilinx Employee
6,649 Views
Registered: ‎03-18-2008

Re: Chipscope <CoreGen>:ERROR:sim:877

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Tallman,

Running the tools as an administrator definitely should be required. Can you open up a webcase with Xilinx Tech Support so that we can look into this further. From the error message, there is a log file that should have more info. Please attach this log file to the webcase:
**See CoreGen Log D:\sil\_ngo\cs_ila_pro_0\coregen.log

Thanks
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Xilinx Employee
Xilinx Employee
6,648 Views
Registered: ‎03-18-2008

Re: Chipscope <CoreGen>:ERROR:sim:877

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**I meant should not be required above...
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