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hacmachdien
Participant
Participant
8,498 Views
Registered: ‎04-04-2013

Chipscope pro data capture

I'm current working on a project that uses the TI ths1206 ADC to sample a 50 hertz alternative current. I'm using a 20 MHz global clock, and the sampling frequency of the ADC   is 5 MHz  which is derived from the global clock. Can i use chipscope pro to visualize the current by using samples obtained from the ADC? btw, what is the sampling frequency of the ILA core, and since I have 2 types of clock, do I have to create 2 ILA cores?

 

PS: sorry for my English ^^!

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

> Can i use chipscope pro to visualize the current by using samples obtained from the ADC?

ChipScope does have some graphing capabilities, so this should be possibe.

 

> what is the sampling frequency of the ILA core

This is determined by the clock that you connect to the ILA core CLK port.

 

> and since I have 2 types of clock, do I have to create 2 ILA cores?


The ILA core CLK must be the same clock that is used for the inputs to the TRIG and DATA ports.  

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hacmachdien
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Registered: ‎04-04-2013

Thank you for your quick reply. There's another question: If I choose the 20 MHz as my ILA's clock then the ILA core should show all the data sampled by the 5 MHz ADC, right?

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

If the 20MHz clock is the one that is used for the ADC interface and clocks in the data then that is the clock that should be used for the ILA core.
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hacmachdien
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Registered: ‎04-04-2013

Can anyone show me the reason why signals of an entire HDL module vanish from the net list of Chipscope pro?

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mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Can you explain what you mean by "vanish"?

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