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coreyhahn
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Registered: ‎09-13-2018

Chipscope: "clock has stopped. Unable to arm ILA core."

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zynq zu19 design

i want to monitor an axi stream with 32 bits of tdata and a tvalid with an ILA core in the BD framework.

I get the error:  "[Labtools 27-3428] Ila core [hw_ila_1] clock has stopped. Unable to arm ILA core.."

I have another ILA core in the same BD on the same clock bus watching an AXI_LITE bus with no problem.

I implemented a counter to blink an led and the clock is on and functioning.

Normally this is a slick implementation.  I have used this debuging use case dozens of times before,

Ideas?

 

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coreyhahn
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Registered: ‎09-13-2018

This was not the case.  But I will keep it in mind in the future!  It turns out that after boot of the Zynq chip I was manually reseting an external clock generation chip.  This is what was causing the chipscope/hardware manager ila to lose it's clock.  Changing my order of operations after boot has allowed the ila core to not lose its clock.  I wish this was not the case but it works.

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mattwaltz
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Registered: ‎06-05-2017

Generally this is caused by the JTAG frequency being set too high. You can follow the settings in UG908 below (Chapter 4: Reconnecting to a Target Device with a Lower JTAG Clock Frequency)

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug908-vivado-programming-debugging.pdf

I hope this helps!

coreyhahn
Contributor
Contributor
2,296 Views
Registered: ‎09-13-2018

This was not the case.  But I will keep it in mind in the future!  It turns out that after boot of the Zynq chip I was manually reseting an external clock generation chip.  This is what was causing the chipscope/hardware manager ila to lose it's clock.  Changing my order of operations after boot has allowed the ila core to not lose its clock.  I wish this was not the case but it works.

View solution in original post

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