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elitezhe
Participant
Participant
15,452 Views
Registered: ‎01-10-2014

Chipscope sample buffer is full

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Hello,

 

I use Chipscope to monitor a axi stream signal, but when i run chipscope to caputure waveform, this information appears.

Unnamed QQ Screenshot20140420182327.png

My board is Digilent Atyls, and My ISE is 14.7 nt64, os:win7 x64

 

These are some pictures of my chipscope settings, can someone help me find where this problem come from?

 

Unnamed QQ Screenshot20140420182354.png

 

 

Unnamed QQ Screenshot20140420182411.png

 

 

Unnamed QQ Screenshot20140420182423.png

 

 

Unnamed QQ Screenshot20140420182510.png

 

Unnamed QQ Screenshot20140420182456.png

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gszakacs
Instructor
Instructor
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Registered: ‎08-14-2007

I'm not really sure I understand your question.  ChipScope can theoretically use as much BRAM as you have left over after building your design.  You could look at the Map report (<project_name>.mrp) to see how many block RAMs are already used and how many remain available.  If your EDK design has a large amount of BRAM you may not have very much left for ChipScope.  Remember that the width of the data port of the ChipScope ILA determines how many BRAMs it takes to make up each 1024 of buffer.  Also ChipScope only supports buffer depths of a power of 2.  So even if you have enough BRAM to make a 3K deep buffer, you won't be able to use more than 2K, for example.

 

If this doesn't answer your question, I'd suggest starting a new thread in the Embedded forums where more people would be acquainted with the EDK tools and might have a better explanation of how to integrate ChipScope to get the most buffer depth.

-- Gabor

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gszakacs
Instructor
Instructor
15,447 Views
Registered: ‎08-14-2007

The messages you posted are perfectly normal for a run where you actually capture data in ChipScope.  So what isn't working that makes you think this was an error?  Are you not seeing the captured waveform?

-- Gabor
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elitezhe
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Participant
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Registered: ‎01-10-2014

Yes, Thank you Gabor,

I make a mistake.

It is not error, i can capture data in waveform.

 

Because i cannot caputure enough points to show a useful timing sequence, i thought it was chipscope problem, but it is not.

 

This "Sample buffer is full" should be an indicator to tell me you can see the waveform , data captured are there.

Am i right?

 

-Zhang Zhe

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gszakacs
Instructor
Instructor
15,416 Views
Registered: ‎08-14-2007

Yes, that's right.  ChipScope will not upload a partial buffer.  So especially when you have storage qualification, it can take time to fill the buffer after receiving a trigger.  Storage qualification can be a good way to display information from a longer time period, but you need to be careful to find a storage qualification condition that gives you everything you want to see without capturing too much data that you don't need.  Often it helps to use multiple match units to create the storage qualifier.  If that doesn't work well enough, you can also try to generate your own logic with the design to produce a signal that will work well.  In that case you would need to use a KEEP attribute on the signal to make sure it is available for ChipScope after the design is translated.  Other than that, you can go back and make a larger buffer for ChipScope if you have more block RAM available.

-- Gabor
elitezhe
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Participant
15,414 Views
Registered: ‎01-10-2014

Thanks Gabor,

 

I have another question.

 

I found that when I try to expand Chipscope buffer from 1024 to a larger number, it may cause EDK error: platgen error.

Only if I decrease the buffer number, EDK will successfully Generate Netlist and Bitstream.

 

The maxium buffer number in my design is 4096(or 2048, I donot remember exactly)

 

I wonder what decide the maxium buffer number?  My FPGA's block RAM size or BRAM control Size of my Design?

 

-Zhang Zhe

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gszakacs
Instructor
Instructor
24,934 Views
Registered: ‎08-14-2007

I'm not really sure I understand your question.  ChipScope can theoretically use as much BRAM as you have left over after building your design.  You could look at the Map report (<project_name>.mrp) to see how many block RAMs are already used and how many remain available.  If your EDK design has a large amount of BRAM you may not have very much left for ChipScope.  Remember that the width of the data port of the ChipScope ILA determines how many BRAMs it takes to make up each 1024 of buffer.  Also ChipScope only supports buffer depths of a power of 2.  So even if you have enough BRAM to make a 3K deep buffer, you won't be able to use more than 2K, for example.

 

If this doesn't answer your question, I'd suggest starting a new thread in the Embedded forums where more people would be acquainted with the EDK tools and might have a better explanation of how to integrate ChipScope to get the most buffer depth.

-- Gabor

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sampatd
Scholar
Scholar
15,394 Views
Registered: ‎09-05-2011
ChipScope requires BRAMs to store the samples captured. Consequently, if you increase the number of samples the BRAM utilization in your design increases. As in the above screenshot, you can check the number of BRAMs getting utilized when the number of samples increases.

Can you check what is the BRAM utilization in your design?

If you have already used some BRAMs for other purposes, you may not be able to increase the number of samples.
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elitezhe
Participant
Participant
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Registered: ‎01-10-2014

Yeah, Thank you .

 

I found the BRAM utilization when I add chipscope core in XPS --> Debug --> Debug Configuration.

 

And in design summary , there is bram utilization data, though i am not sure i really understand those numbers and percentage means.

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