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abc2005211
Visitor
Visitor
3,869 Views
Registered: ‎03-13-2013

Could not use chipscope to watch the ISERDES2 data output.

I use xapp1064 as base to initialize my project with sp6, but when i add chipscope to watch the data output of iserdes2 the route failed with unroted signals report. And without the chipscope core , the project could generate bit stream successfully. 

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5 Replies
balkris
Xilinx Employee
Xilinx Employee
3,863 Views
Registered: ‎08-01-2008

what error message you are getting . Can you please explore little more. I would say check the warning/error and try to fix it
Thanks and Regards
Balkrishan
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abc2005211
Visitor
Visitor
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Registered: ‎03-13-2013

thanks !

 

this is the report!

 

Release 14.5 - par P.58f (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.

Thu Mar 16 11:41:04 2017

121 signals are not completely routed.

WARNING:ParHelpers:360 - Design is not completely routed.

GLOBAL_LOGIC1
N124
N180
N181
N20
N22
N36
N38
N40
N44
N46
N48
N50
N52
N56
N58
u1/diff_rx/inst_clkin/ddly_m
u1/diff_rx/inst_clkin/ddly_s
u1/diff_rx/inst_clkin/rx_bufio2_x1
u1/diff_rx/inst_clkin/rx_clk_in_n
u1/diff_rx/inst_clkin/rx_clk_in_p
u1/diff_rx/inst_datain/busy_data<0>
u1/diff_rx/inst_datain/busy_data<1>
u1/diff_rx/inst_datain/cascade<0>
u1/diff_rx/inst_datain/cascade<1>
u1/diff_rx/inst_datain/ddly_m<0>
u1/diff_rx/inst_datain/ddly_m<1>
u1/diff_rx/inst_datain/ddly_s<0>
u1/diff_rx/inst_datain/ddly_s<1>
u1/diff_rx/inst_datain/incdec_data<0>
u1/diff_rx/inst_datain/incdec_data<1>
u1/diff_rx/inst_datain/loop0[0].data_in/SLAVEBUF.DIFFIN
u1/diff_rx/inst_datain/loop0[1].data_in/SLAVEBUF.DIFFIN
u1/diff_rx/inst_datain/pd_edge<0>
u1/diff_rx/inst_datain/pd_edge<1>
u1/diff_rx/inst_datain/pd_state_machine/GND_21_o_busy_data_d_OR_182_o
u1/diff_rx/inst_datain/pd_state_machine/Mcount_counter_cy<3>
u1/diff_rx/inst_datain/pd_state_machine/Mcount_counter_cy<7>
u1/diff_rx/inst_datain/pd_state_machine/Mmux_pdcounter[4]_pdcounter[4]_mux_52_OUT_rs_cy<3>
u1/diff_rx/inst_datain/pd_state_machine/Mmux_pdcounter[4]_pdcounter[4]_mux_59_OUT21
u1/diff_rx/inst_datain/pd_state_machine/_n0175
u1/diff_rx/inst_datain/pd_state_machine/_n0187_inv
u1/diff_rx/inst_datain/pd_state_machine/_n0190_inv
u1/diff_rx/inst_datain/pd_state_machine/busy_data_d
u1/diff_rx/inst_datain/pd_state_machine/cal_data_master
u1/diff_rx/inst_datain/pd_state_machine/cal_data_sint
u1/diff_rx/inst_datain/pd_state_machine/ce_data<0>
u1/diff_rx/inst_datain/pd_state_machine/ce_data<1>
u1/diff_rx/inst_datain/pd_state_machine/ce_data_inta
u1/diff_rx/inst_datain/pd_state_machine/counter<0>
u1/diff_rx/inst_datain/pd_state_machine/counter<10>
u1/diff_rx/inst_datain/pd_state_machine/counter<11>
u1/diff_rx/inst_datain/pd_state_machine/counter<11>_inv
u1/diff_rx/inst_datain/pd_state_machine/counter<1>
u1/diff_rx/inst_datain/pd_state_machine/counter<2>
u1/diff_rx/inst_datain/pd_state_machine/counter<3>
u1/diff_rx/inst_datain/pd_state_machine/counter<4>
u1/diff_rx/inst_datain/pd_state_machine/counter<5>
u1/diff_rx/inst_datain/pd_state_machine/counter<6>
u1/diff_rx/inst_datain/pd_state_machine/counter<7>
u1/diff_rx/inst_datain/pd_state_machine/counter<8>
u1/diff_rx/inst_datain/pd_state_machine/counter<9>
u1/diff_rx/inst_datain/pd_state_machine/inc_data_int
u1/diff_rx/inst_datain/pd_state_machine/inc_data_int_d<0>
u1/diff_rx/inst_datain/pd_state_machine/inc_data_int_d<1>
u1/diff_rx/inst_datain/pd_state_machine/incdec_data_d
u1/diff_rx/inst_datain/pd_state_machine/mux<0>
u1/diff_rx/inst_datain/pd_state_machine/mux<1>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter<0>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter<1>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter<2>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter<3>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter<4>
u1/diff_rx/inst_datain/pd_state_machine/pdcounter[4]_GND_21_o_equal_46_o
u1/diff_rx/inst_datain/pd_state_machine/pdcounter[4]_PWR_20_o_equal_45_o
u1/diff_rx/inst_datain/pd_state_machine/rst_data
u1/diff_rx/inst_datain/pd_state_machine/state_FSM_FFd1
u1/diff_rx/inst_datain/pd_state_machine/state_FSM_FFd2
u1/diff_rx/inst_datain/pd_state_machine/state_FSM_FFd3
u1/diff_rx/inst_datain/pd_state_machine/state_FSM_FFd4
u1/diff_rx/inst_datain/pd_state_machine/valid_data_d
u1/diff_rx/inst_datain/rx_data_in<0>
u1/diff_rx/inst_datain/rx_data_in<1>
u1/diff_rx/inst_datain/valid_data<0>
u1/diff_rx/inst_datain/valid_data<1>
u1/diff_rx/rx_bufg_x1
u1/diff_rx/rx_serdesstrobe
u1/diff_rx/rxd<0>
u1/diff_rx/rxd<1>
u1/diff_rx/rxioclkn
u1/diff_rx/rxioclkp
u1/diff_rx/rxr<0>
u1/diff_rx/rxr<1>
u1/diff_rx/rxr_0_1
u1/diff_rx/rxr_1_1
u1/spi_inst/spi_inst/cstate[7]_GND_11_o_equal_27_o/ProtoComp29.C5LUT.O5
u1/spi_inst/spi_inst/cstate_c<0>
u1/spi_inst/spi_inst/cstate_c<1>
u1/spi_inst/spi_inst/cstate_c<2>
u1/spi_inst/spi_inst/cstate_c<3>
u1/spi_inst/spi_inst/spi_tx_data_ff<235>
u1/spi_inst/spi_inst/spi_tx_data_ff<236>
u1/spi_inst/spi_inst/spi_tx_data_ff<243>
u1/spi_inst/spi_inst/spi_tx_data_ff<244>
u1/spi_inst/spi_inst/spi_tx_data_ff<245>
u1/spi_inst/spi_inst/spi_tx_data_ff<247>
u1/spi_inst/spi_inst/spi_tx_data_ff<248>
u1/spi_inst/spi_inst/spi_tx_data_ff<249>
u1/spi_inst/spi_inst/spi_tx_data_ff<250>
u1/spi_inst/spi_inst/spi_tx_data_ff<251>
u1/spi_inst/spi_inst/spi_tx_data_ff<253>
u1/spi_inst/spi_inst/spi_tx_data_ff<254>
u1/spi_inst/u0/config_reg_start
u1/spi_inst/u0/cstate[15]_GND_10_o_equal_77_o
u1/spi_inst/u0/cstate[15]_GND_10_o_equal_78_o
u1/spi_inst/u0/cstate_c<0>
u1/spi_inst/u0/cstate_c<1>
u1/spi_inst/u0/cstate_c<2>
u1/spi_inst/u0/cstate_c<3>
u1/spi_inst/u0/cstate_c<4>
u1/spi_inst/u0/spi_tx_start_ff
WARNING:ParHelpers:361 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.

key_i<1>_IBUF

 

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arpansur
Moderator
Moderator
3,842 Views
Registered: ‎07-01-2015

Hi @abc2005211,

 

OSERDES o/p should go to IOB only. You can't probe using chipscope.

Thanks,
Arpan
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abc2005211
Visitor
Visitor
3,833 Views
Registered: ‎03-13-2013

i know that . i did not catch the iob signal into chipscope.

 

i just watch the deser data output signal with div clk.

 

 

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abc2005211
Visitor
Visitor
3,831 Views
Registered: ‎03-13-2013

I am confused when i used the xapp1064 source file. It still fialed to route even if i did not insert ila core.

 

1.jpg
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