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Visitor
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Registered: ‎04-28-2017

Hardware Co-Simulation in Multi Clock System, System Generator

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Hello Forum Members!

 

I am experimenting with System Generator and the Hardware Co-Simulation features. I am curious to know if the hardware co-simulator can work with designs with multiple clock rates. So far, I have not come across anything in the documentation that says this is not possible.   

 

I have been using the tutorials for UG948 to run these tests. HW cosim works great with my zedboard on lab1_3_sol.slx, but I run into some errors when I test it on lab3_3_sol.slx, the first multi clock rate tutorial.

 

I have narrowed it down to an error in the log file. It seems to be happening when sysgen invokes Vivado to start creating the wrapper and code for my zedboard. There are some forum posts for what to do to when this occurs in vivado, but I don't seem to have the same flexibility in sysgen that is available in vivado. 

ERROR: [IP_Flow 19-3458] Validation failed for parameter 'AXI Address Width(C_AXI_ADDR_W)' for BD Cell 'hwcosim_cmd_proc'. Value '3' is out of the range (4,32)
INFO: [IP_Flow 19-3438] Customization errors found on 'hwcosim_cmd_proc'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Validation failed for parameter 'AXI Address Width(C_AXI_ADDR_W)' for BD Cell 'hwcosim_cmd_proc'. Value '3' is out of the range (4,32)
Customization errors found on 'hwcosim_cmd_proc'. Restoring to previous valid configuration.

INFO: [Common 17-17] undo 'set_property'
ERROR: An error occurred when creating the Vivado project.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Thu May 04 16:56:08 2017...

Ultimately, I just want to know if this is possible. Has anyone else been able to use hardware co-simulation in Sysgen that included multiple clock domains? If so, what did the system look like? 

 

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Visitor
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Registered: ‎04-28-2017

I have found the answer to my own question. 

The System Generator User Guide UG897 has a "known issue" listed on page 98 under the Multiple Independent Clocks Hardware Design. This is what it says:

 

"The HWCosim Compilation Target is not supported for Multiple Clock Designs."

 

So, there you go. It is not possible.

 

A workaround for anyone interested is to Cosim each subsystem individually and sequentially test the whole system one clock rate at a time. 

 

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Visitor
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3,826 Views
Registered: ‎04-28-2017

I have found the answer to my own question. 

The System Generator User Guide UG897 has a "known issue" listed on page 98 under the Multiple Independent Clocks Hardware Design. This is what it says:

 

"The HWCosim Compilation Target is not supported for Multiple Clock Designs."

 

So, there you go. It is not possible.

 

A workaround for anyone interested is to Cosim each subsystem individually and sequentially test the whole system one clock rate at a time. 

 

View solution in original post

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