04-27-2017 08:53 AM
I've encrypted an VHDL module using IEEE1735 in Vivado 2016.4
Now, I want to create a netlist of this encrypted VHDL. I've got following error (when running write_edif)
ERROR: [Designutils 20-2284] Design protected by IEEE 1735 V2 may not be written to EDIF
When looking at ug1118 table 6-2, it seems to be possible to add Xilinx Specific Tool Rights to enable netlist creation
Is Vivado allowed to export a netlist of protected region? “true”, “false”
It should be true by default but even by setting it to true it does'nt work (Error described above).
04-27-2017 09:28 AM
I think you cannot use IEEE1735 encryption on an EDIF file. The workaround would be to use write_vhdl or write_verilog instead to have the synthesized design.
04-27-2017 09:49 AM
Popular netlist formats, like EDIF, are not covered by IEEE 1735
-> so if you could write an edif, it won't be encrypted... so it would make no sense to encrypt the file from the beginning...
So the answer is only that you cannot write an edif on encrypted source. You can only write verilog (and systemVerilog) or vhdl
04-27-2017 10:13 AM
What is said in ug1118 is
"Although there are many different formats of design source files, IEEE-1735-2014 only applies to Verilog, SystemVerilog, and VHDL formats. These RTL standards are also governed by the IEEE, and it is by mutual agreement that those standards will allow IEEE-1735 to define behavior in IP security until such a time as the recommendations in IEEE 1735 can be retrofitted into the original language standards contained in the language reference manuals (LRMs). Popular netlist formats, like EDIF, are not covered by IEEE 1735."
According to my understanding, it talks about source to encrypt. And what I'm encrypting is VHDL.
My problem is not with encrypt Tcl command but with write_edif tcl command after having encrypted my VHDL source file.
It is not very clear if it means that EDIF cannot be generated after encryption.
Concerning write_edif, It seems to be compatible with encrypted files since on option is available for that purpose
[-security_mode] If set to 'all', and some of design needs encryption then whole of design will be written to a single encrypted file.
I will try with write_vhdl, and let you know, but I'm interested in knwoing your opinion concerning my above questionning.
06-27-2018 04:32 PM
I wondered what did you get on with this?
So far we have tried two approaches
1. Encrypt all source files first using `encrypt -key key_file -lang verilog -ext .svp <file_name.sv>`, run synthesis, and `write_edif -security_mode all <netlist.edn>` to get a single specified encrypted EDIF file.
We did more or less the same as your last post but doesn't seem to get us to anywhere. It would be great if you could share your experience here.