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5,785 Views
Registered: ‎04-24-2016

ILA Debug Core not detected

i have use ILA ip core to debug my design and it works, but next day, i tried to download the program again into FPGA but it didn't work and i got the following message after programing the FPGA:

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WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7k160t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7k160t_0 and the probes file D:/MPSK_Classification_Whole_Feedback_Demod_PR1_PRC/MPSK_Classification_Whole.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 6 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

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- i tried the first and second resolution but every time i get the same message.

- i changed the C_USER_SCAN_CHAIN property to 1,2,3, and 4 but got the same message.

- i tried this command [-e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>"] but i got message :

invalid command name "-e".

- the bit file and ltx file are the suitable files, it was working before, but suddenly stop working.

 

Can you help me?

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Moderator
Moderator
5,750 Views
Registered: ‎09-15-2016

Hi mo7amed_elhady@yahoo.com,

 

Please check if this AR#58406 helps: https://www.xilinx.com/support/answers/58406.html.

 

Regards,
Prathik
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Moderator
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5,739 Views
Registered: ‎07-01-2015

Hi mo7amed_elhady@yahoo.com,

 

  1. Please check the clock connectivity. The clock should be free running. In most of the cases this is the issue.
  2. Check if there are any timing violations in the design.
  3. Make sure the JTAG clock frequency is less than or equal to half of ILA clock frequency.
Thanks,
Arpan
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Moderator
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5,729 Views
Registered: ‎09-15-2016

Hi mo7amed_elhady@yahoo.com,

 

Can you please check if the below Answer record helps:

https://www.xilinx.com/support/answers/64764.html

 

Thanks & Regards,

Sravanthi B

 

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Thanks & Regards,
Sravanthi B
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5,709 Views
Registered: ‎04-24-2016

Hello prathikm arpansur,

 

- i changed the C_USER_SCAN_CHAIN property to be 1,2,3, and 4 but got the same message.

- i tried to Manually launch hw_server in the Windows command prompt:

 hw_server  -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN 2>

but i got the message as in the photo.

- i'm tired to make ILA debug core work, do you have additional solutions??

thank you in advance

note:

i have others (two or three) vivado VHDL programs that use ILA debug core in their designs and it works probably.

Untitled.png
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5,159 Views
Registered: ‎05-09-2014

Bandi Prathikm

 

     I have exactly the same problem now.  I tried everything you did but nothing seem to work.  Did you ever solve the problem and how did you solve it?  I'm also using Vivado 2015.4 on a VC707 Eval Board.

 

     In my case I'm using the ILA insertion feature by opening the Synthesized design and using the Set Up Debug option.  After the design is processed I open the Implemented design and my ILA cores are shown.  The FPGA runs fine, I use the Hardware Manager to program the device and it always works.

 

     Any news would be very helpful.

 

        Marv

 

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Participant
Participant
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Registered: ‎10-07-2016

There's a closing quote missing on starting the hw_server in a command window. This IS in the answer record too. AR# 64764 at the bottom in step 3.
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