UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
1,331 Views
Registered: ‎08-10-2017

ILA core not recognized by hardware manager VC707

 Hi

I'm using VC707 having Virtex7 485T FPGA.  and using Vivado 2017.2

I generated the following block design a custom Master AXI-Lite Controller. I'm using ILAs at 

  1. AXI-Lite and AXI Interconnect
  2. AXI Interconnect and AXI BRAM Controller
  3. AXI BRAM Controller and Block Memory Generator

I got the warning 

The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7vx485t_0 and the probes file(s) /media/cn1lab005/dataFYP/vivado_projects/fyp/MASTER_AXI_ACC/axilite_test/axilite_test.runs/impl_1/top.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 3 ILA core(s) and 0 VIO core(s).
Resolution: 
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

bd.png

The "clk" input is single ended 200 MHz clock generated from System Clock (differential, 200 MHz (SYSCLK_P and SYSCLK_N)) using Clocking Wizard. The locked output of Clocking Wizard is HIGH . It is connected to ILA 0 and ILA 1. Is this clk free-running ? Can I use it for ILA ? 

 

The "axi_aclk" is 250 MHz. This is connected to ILA 2. Even this ILA was not detected. (Btw, user_link_up is HIGH when I turn on the PC after programming the bitstream). ("pcie_reset" is connected to one of the push buttons)

 

I followed similar posts like

I also tried 

  1. JTAG frequency is now 1.5 MHz (much lower than ``clk" frequency used)
  2. I created a fresh project (as mentioned in one of the posts) and implemented the design again. And yet, ILA cores weren't detected.

Note : There are no timing errors in the design.

 

I'm going to try modifying the scan chain settings mentioned in the warning. (changing to scan chain 2 instead of 1 or 3). I wanted to ask the community whether it is wise to modify the setting before doing it ? 

 

If I'm doing something wrong, please correct me.

 

 

Thank You

 

 

Jagannath

0 Kudos
5 Replies
Contributor
Contributor
1,298 Views
Registered: ‎10-31-2017

Re: ILA core not recognized by hardware manager VC707

Hello.

Could you share your xdc file?

find clock connected to the dbg_hub.

 

In XDC you can try change clock for debug hub. Sometimes this helps.

 

--

Sorry for my English

0 Kudos
Moderator
Moderator
1,283 Views
Registered: ‎10-19-2011

Re: ILA core not recognized by hardware manager VC707

No it does not sound like that clock is free running. The debug hub has a hard time recovering from a stopped clock at initialization, you can try a refresh, but its possible it will not recover.
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Contributor
Contributor
1,271 Views
Registered: ‎10-31-2017

Re: ILA core not recognized by hardware manager VC707

Maybe You fortgot to set ila unints in postsynhesys debug window ? :)

0 Kudos
Highlighted
Adventurer
Adventurer
1,257 Views
Registered: ‎08-10-2017

Re: ILA core not recognized by hardware manager VC707

@mkorobkov 

 

find clock connected to the dbg_hub

 

I found the clock connected to system_ila_0 (and system_ila_1) in the Implemented Design. It is connected to output of Clocking Wizard.

 

Maybe You fortgot to set ila unints in postsynhesys debug window ? 

 

I followed this video https://www.xilinx.com/video/hardware/axi-interface-debug-using-vivado-ip-integrator.html

Post Synthesis flow for setting up debug is not required.

 

 

@travisc

 

 it does not sound like that clock is free running

 

VC707 has LVDS clock inputs (system Clock). How else should I connect it to ILA without converting it to single ended clock ?

0 Kudos
Contributor
Contributor
1,251 Views
Registered: ‎10-31-2017

Re: ILA core not recognized by hardware manager VC707

Could you  to share the design? 

0 Kudos