06-20-2018 05:03 AM - edited 06-20-2018 05:20 AM
I'm using VC707 having Virtex7 485T FPGA. and using Vivado 2017.2
I generated the following block design a custom Master AXI-Lite Controller. I'm using ILAs at
I got the warning
The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7vx485t_0 and the probes file(s) /media/cn1lab005/dataFYP/vivado_projects/fyp/MASTER_AXI_ACC/axilite_test/axilite_test.runs/impl_1/top.ltx. The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 3 ILA core(s) and 0 VIO core(s). Resolution: 1. Reprogram device with the correct programming file and associated probes file(s) OR 2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.
The "clk" input is single ended 200 MHz clock generated from System Clock (differential, 200 MHz (SYSCLK_P and SYSCLK_N)) using Clocking Wizard. The locked output of Clocking Wizard is HIGH . It is connected to ILA 0 and ILA 1. Is this clk free-running ? Can I use it for ILA ?
The "axi_aclk" is 250 MHz. This is connected to ILA 2. Even this ILA was not detected. (Btw, user_link_up is HIGH when I turn on the PC after programming the bitstream). ("pcie_reset" is connected to one of the push buttons)
I followed similar posts like
I also tried
Note : There are no timing errors in the design.
I'm going to try modifying the scan chain settings mentioned in the warning. (changing to scan chain 2 instead of 1 or 3). I wanted to ask the community whether it is wise to modify the setting before doing it ?
If I'm doing something wrong, please correct me.
06-20-2018 07:52 AM
Could you share your xdc file?
find clock connected to the dbg_hub.
In XDC you can try change clock for debug hub. Sometimes this helps.
Sorry for my English
06-20-2018 01:45 PM
06-21-2018 04:29 AM
find clock connected to the dbg_hub
I found the clock connected to system_ila_0 (and system_ila_1) in the Implemented Design. It is connected to output of Clocking Wizard.
Maybe You fortgot to set ila unints in postsynhesys debug window ?
Post Synthesis flow for setting up debug is not required.
it does not sound like that clock is free running
VC707 has LVDS clock inputs (system Clock). How else should I connect it to ILA without converting it to single ended clock ?