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27,375 Views
Registered: ‎04-04-2014

ILA issues with Vivado 2014.3

I have been trying to run the Avnet Zedboard lab regarding the 802.11 Beacon frame receiver.

http://zedboard.org/course/integrated-software-defined-radio-zynq%C2%AE-7000-all-programmable-soc

 

I have gotten through all the lab work and am ready now to debug my bit stream using the ILA tool.

 

dbg_hub and ila are clearly visible in the synthesized and implemented design, but when I load the bitstream I get the following warning messages:

 

refresh_hw_device [lindex [get_hw_devices] 1]
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped.
INFO: [Labtools 27-1434] Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. You must manually launch hw_server
with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4.
To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file D:/Avnet/Zynq_SDR_2014/vivado/fmcomms2_zed_802_11_RX/fmcomms2_zed_802_11_RX.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 2 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file OR
2. Goto device properties and associate the correct probes file with the programming file already programmed in the device.

 

 

So I ran :

get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]
1

 

As recommended, I reduced my JTAG clock speed to 3MHz and it did not do anything either.

 

I also went back to Vivado 2014.3 - same problem.

 

So far no luck, and I have been at this for three days now - very frustrating.

You cannot use an IDE without proper debugginh tool.

 

Am I the only one having these issues? I see there were similar problems with Vivado 2013.3 about a year ago.

But yet not fixed???

 

Arne

 

 

 

 

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13 Replies
martinal
Visitor
Visitor
27,320 Views
Registered: ‎07-08-2013

I was having the same problem. Just figured out my issue, maybe it will help yours too.

My ILA clock was being driven by the processor. I would get that error if the processor was loaded with a design from SDK. Once I ran a design in SDK, I would be able to refresh in the hardware manager and see my debug cores.

Hope that helps you too.
martinal
Visitor
Visitor
27,314 Views
Registered: ‎07-08-2013

Let me correct that, I would get that error if the processor WASN'T loaded.
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rholschbach
Visitor
Visitor
27,271 Views
Registered: ‎11-18-2013

I was fighting this same issue, I had it where I was running one of the ILA clock via a external clock running thru a DCM, that can be enabled or disabled, and other ILA clocks were running via the Processor clocks.   The processor I had loaded and running so it appears that the ILA clock being picked to be used by the JTAG $#%$  must have been the external clock in my case.  Of course I did not see this post until just after I resolved the cause of my issue.  Seeing this post sooner would have helped.   With this being a severe weakness in this Debug core Xilinx should at least print out a proper message to indicate a clue of what could be the cause of this issue.

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smitha
Xilinx Employee
Xilinx Employee
27,240 Views
Registered: ‎08-02-2013

Hi

In 2014.3 you will get these warnings if

 

  • the clock connecetd to the debug hub is not free running clock or active
  • the debug hub User Scan Chain setting is 2 or 4 (It is a 1 by default)

 

We did realize that the resolution to this warning needs to be more explicit and have fixed it in 2014.4 as follows:

 

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].

 

Thanks

Smitha

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muvvarao
Visitor
Visitor
24,025 Views
Registered: ‎04-30-2015

so, how to solve the issue, can you please guide with detatils

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sanjivgarg
Adventurer
Adventurer
23,768 Views
Registered: ‎12-10-2014

yes I am having exact same problem with zynq fpga;

how to fix? can you provide step by step instructions?

 

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sriramv90
Visitor
Visitor
23,641 Views
Registered: ‎07-30-2015

Very simple,

 

Just export the hardware to SDK and then open SDK.

 

In SDK run a debug session and start your program by keeping some breakpoint at the start of your program. 

 

You should be able to see the debug core back on the ILA hardware session :)

 

Cheers,


Sriram

arpansur
Moderator
Moderator
23,557 Views
Registered: ‎07-01-2015

If the clock connected to dbg_hub is not free running then you will get this warning. One thing you can try is try to connect the clock of dbg_hub to a free running clock(e.g; sys_clk) on FPGA. Check if it resolves your issues. If it doesn't resolve your issue then open implemented design and check the following command:

get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub] in Tcl console.

 

Thanks,
Arpan
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daniel.kho
Observer
Observer
23,309 Views
Registered: ‎09-19-2012

I have this same problem. The interesting thing is that ISE allowed non-free-running or generated clocks to be used by ILA, but Vivado does not allow this.

 

I need to sample the data every 10480 clock cycles, so I created a frequency divider from my reference clock that divides down by 5240. MMCM is not able (?) to create a divided clock with such a high division ratio. I previously used this divided clock in an ISE design, and it works. However, when migrating to Vivado, the tool seems to require not just a free running clock, but clocks that are not generated from user logic (I used a counter to generate my divided clock).

 

Is there a way to allow the use of generated clocks for ILA in a Vivado design?

 

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jpsaigautam
Visitor
Visitor
9,331 Views
Registered: ‎04-23-2014

I dont know if this helps, but under Debug tab, cell properties, debug core options, there is a C_ENABLE_CLK_DIVIDER option..

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mowerj
Participant
Participant
7,505 Views
Registered: ‎12-28-2014

came across this issue myself (using 2016.4) on a zynq.  I read most of the suggestions here and just in case it was not covered completely - to fun from SDK - just close the hardware in vivado, start the application on the processor, and then re-open hardware.

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anunesgu
Moderator
Moderator
6,654 Views
Registered: ‎02-09-2017

With Zynq7000, when using the PS (Processor) as a clock provider to the PL (FPGA), you must first properly start the PS resources before trying to load and debug a design in the PL. Otherwise, the PL might not receive the clock early enough to start the debug core, and you will see the error messages previously posted.

 

To do so, you must run the ps7_init.tcl command in SDK. The ps7_init files contain the initialization code for the Zynq Processing System and initialization settings for DDR, clocks, plls, and MIOs. SDK uses these settings when initializing the processing system so that applications can be run on top of the processing system. 

 

In the SDK, go to Run -> Debug Configurations

 

SDK menu.jpg

Go to Xilinx C/C++ application (System Debugger) and, If there is no configuration file under it, right-click on it and select “new”.

 

SDK System Debugger.jpg

 

You will see the following window. On Debug Type, select “Standalone Application Debug”.

 

SDK System Debugger(2).jpg

 

Check the boxes “reset Entire System” and “Run ps_init”

SDK System Debugger(3).jpg

 

Under the Application tab, select the option to Download your project .elf file to the PS, and check the box “stop at program entry”. This should fully start the PS and halt it at Main().

SDK System Debugger(4).jpg

 

You can now hit the buttons Apply and then Debug. If everything goes well, you should see the confirming messages.

You can now go back to Vivado, reprogram the FPGA and check if the Debug Core is working.

 

Thank you.

Andre Guerrero

Product Applications Engineer

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wcham
Visitor
Visitor
4,705 Views
Registered: ‎05-21-2018

May be the clock of ila-hub should be activated.  One of method for doing that is making  Zynq processor  start to work.

One of method is running any application by using XSDK. Another method is booting from QSPI flash which is programming to start bist-app program.  After that you try to use hardware manager  to open target. Good Luck!!      

 

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