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Contributor
Contributor
406 Views
Registered: ‎12-10-2018

Instability in ILA signals

Hello everybody!

I'm working with a Kintex-7 FPGA on a custom board with Vivado 2017.4.1. I have several peripeherals like DDR3, AD9361 module, Ethernet, etc. The FPGA design is complex and a significant amount of FPGA resources is used.

I have done simulations as much as possible and everything is correct in simulation. I also have created a design without some of the peripherals and interfaces and programmed that on the board, and again there's no errors.

The problem is when I have a design with all interfaces and program that on the board. There are alot of errors in this case. Naturally I started to debug my design using ILA. But wherever I put ILA in my design (I mean every signal that I see in ILA) there are errors and the root of error can't be found.

To be more specific, I should say that there are times which there's no error but after a short time there are errors, maybe it gets correct without any changes and maybe it continues to having errors. I mean there is not a logical effect and repititive behaviour on signals that I'm looking at in the ILA.

Can anybody help me with this? Does anybody have ever had a similar issue in instable and weird behaviour of signals in Vivado ILA? What are things to be checked out? What could be the problem's root?

I have to note that I have put alot of time to make correct and enough timing constraints in the design. And I have considered issues like input and output delay, CDCs, etc.

Any help is highly appreciated.

Regards,

Herman

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8 Replies
267 Views
Registered: ‎06-21-2017

Re: Instability in ILA signals

One thing you should look at with a custom board is power.  Have you monitored all of the voltages with a scope?  Do any power rails droop with a fully loaded design?  Do they get noisy? 

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Scholar drjohnsmith
Scholar
265 Views
Registered: ‎07-09-2009

Re: Instability in ILA signals

How are you taking care of and constraining the metastabilty and asynchronous interfaces ?

Is the design fully constrained and meets the constraints ?

can we have copy of your constraints file please
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Contributor
Contributor
206 Views
Registered: ‎12-10-2018

Re: Instability in ILA signals

Thanks for your reply Bruce!
Yes, I have monitored all the voltages before and after FPGA program. And there's not any noises or ripples and the voltages are stable. So this seems not to be the problem!
Do you have any other ideas about other sources which can lead to such a problem? Have you ever had a similar issue?
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Highlighted
Contributor
Contributor
206 Views
Registered: ‎12-10-2018

Re: Instability in ILA signals

Thanks for your reply John!
I have added FIFOs for CDC paths and I have added input and output delays just as the datasheet says. I have also added constraints for the asynchronous clocks.
I think the design is fully constrained and all the constraints are met. Do you have any specific issue same as mine? I mean do you think the reason is that constraints are not enough and this can lead to unstable and weird behavior in ILA signals? Do you have any ideas what to do or what to check in this circumstance?
And about the last part of your answer: I'm so sorry I can't disclose the files because of company rules. But I really need help and if you can tell me what are things to check? Thanks...
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Scholar drjohnsmith
Scholar
198 Views
Registered: ‎07-09-2009

Re: Instability in ILA signals

Sorry

 

the problem you have is in the desing and constraints,

 

Without these were guessing and possibly leading you down the worng path making things worse.

An over constrained design is as bad ( IMHO ) as an under constrained one,

 

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Contributor
Contributor
180 Views
Registered: ‎12-10-2018

Re: Instability in ILA signals

So you definitely think that this kind of behavior is related to timing constraints?
My design has the following constraints:
- clocks definition and max delay for CDC paths
- input and output delays
Is there any other general timing constraints which is not involved above?
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Scholar drjohnsmith
Scholar
175 Views
Registered: ‎07-09-2009

Re: Instability in ILA signals

Sorry

 

the problem you have is in the desing and constraints,

 

Without these were guessing and possibly leading you down the worng path making things worse.

An over constrained design is as bad ( IMHO ) as an under constrained one,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer sarman_1998
Observer
159 Views
Registered: ‎05-16-2018

Re: Instability in ILA signals

Another possibility that come to mind is interference between signals on your board.

Can you be any more specific about the errors you are seeing?

Have you tried to determine what part of the design that is in the full image but not in your partial image causes the issue?

Have you checked your CDC reports?

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