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mdomingu
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Registered: ‎07-10-2018

Issue while programming a bitstream with ILA

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Hello,

I am trying to debug an application to which I added an ILA, I generated the bitstream and then tried to program it into the PL of my ZedBoard via Vivado. The problem is that as soon at it finishes, a warning is prompted, which is:

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device.  To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3403] Dropping logic core with cellname:'Application_design_i/system_ila_0/U0/ila_lib' from probes file, since it cannot be found on the programmed device.

So, the first thing I did was searching on the internet, where I found this link http://www.xilinx.com/support/answers/64764.html . I opened the synthesis design and followed the steps, but I couldn't see whether my clock signal was a free running clock or not, I decided to take another clock signal and of the design and use it for my ILA and dbg_hub, despite this, it still did not work. So I went through the step of launching manually a hardware server to change the C_USER_SCAN_CHAIN property (which I don't know what it is...), but in my Linux terminal the hw_server command is not found. Now that the context was explained here comes my questions:

  • How I know whether or not a clock is a free running one?
  • Why I don't have the pretty undocumented hw_server command? Where can I obtain it?
  • What is the C_USER_SCAN_CHAIN property?

Thank you in advance for you attention and sorry if I did not make myself clear, I am pretty new to these kind of tools,

Marc

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arpansur
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2,388 Views
Registered: ‎07-01-2015

Hi @mdomingu,

 

In case you are using PS clock, then did you initialize the PS?

You have to initialize the PS using ps_init.tcl. Then the clock will be available.

Then you can program PL using bitstream. 

Thanks,
Arpan
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6 Replies
jmcclusk
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Registered: ‎02-24-2014

I've seen this happen when Vivado digs around in the netlist and connects the clock input of the debug hub to the first clock it finds...  which may or may not be actually an active clock at the moment the design is loaded.   I've worked around this by implementing a short TCL script that disconnects the debug hub clock, and then reconnects it to a known good clock net in the design.   This script is typically run before placement, but after opt_design.    

 

you don't want a high speed clock for the debug hub... In the range of 30 to 60 MHz is nice.  There should be something coming out of your ps7 block that's usable.

 

In any event,  your problems are addressed by AR#64764.     It's hard to explain why you didn't find the hw_server command.  Did you run the settings64.sh script first to setup the Xilinx environment when you opened a terminal?

Don't forget to close a thread when possible by accepting a post as a solution.
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mdomingu
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Registered: ‎07-10-2018

Thank you for your answer.

Yes, I saw this link and I tried it. The first option of changing the clock did not work (also I was not sure if it was a free running clock or not, because there is no such option...), so I was going to try the hw_server option. As you told me, I didn't execute the settings64.sh (how I would have known this?), so I did it  and tried with this but did not work. Now I disconnected the debug hub clock and tried the following:

connect_debug_port dbg_hub/clk [get_nets Application_design_i/processingSystem7/PS_CLK]

But this critical warning is prompted,

CRITICAL WARNING: [Chipscope 16-3] Cannot debug net 'Application_design_i/processingSystem7/PS_CLK'; it is not accessible from the fabric routing.

So... which clock should I use?

Marc

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iguo
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008
Do you have an external oscillator on board with FPGA? If so, try with that clock for ILA. If the clock you used for ILA needs to get locked first or it cannot be stable until some delay after Configuration, ILA won't be detected and the error popped up as you posted.
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mdomingu
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Registered: ‎07-10-2018

My board is a ZedBoard Zynq7000, I think that the unique "external clock" I have is the PS one, but as I said above I couldn't use it. Sorry if I get harsh but I am pretty new with this, I used Altera tools before but they are not similar to the Xilinx ones.

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arpansur
Moderator
Moderator
2,389 Views
Registered: ‎07-01-2015

Hi @mdomingu,

 

In case you are using PS clock, then did you initialize the PS?

You have to initialize the PS using ps_init.tcl. Then the clock will be available.

Then you can program PL using bitstream. 

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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mdomingu
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Registered: ‎07-10-2018

The PS was not powered on, only the PL, so it's normal that no free running clock existed, there was no clock!!! The jumpers were not in the state they had to be, so the processor was never booted, :) . Thank you for your help.

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