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Newbie
Newbie
10,052 Views
Registered: ‎10-13-2014

Issue with COE file in Xilinix IP Cores

Hi,

 

Currently i am using FIR and BLOCK RAM IP Cores of Xilinx. When i tried to add .coe file to the core it is taking succesfully and it could perform synthesis. When i do re-synthesis it is giving error as "having problem in reading .coe file". The coe files are kept in root location of project folder. 

 

If anyone faced similar problem and resolved, then please let me know the work around.

 

Thanks in advance for your assistance.

 

--Aravind 

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Xilinx Employee
Xilinx Employee
10,047 Views
Registered: ‎09-20-2012

Hi @aravindslm

 

Customize the block memory generator IP and click on browse option beside the COE file and located the COE file. Generate the IP and see if it helps.

Thanks,
Deepika.
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