01-28-2021 07:12 AM
I would like to know when the JTAG to AXI Master IP will be available for the Versal part?
02-01-2021 09:57 AM
UG1273 states : "The JTAG-to-AXI soft debug IP is no longer offered as an option in the Versal ACAParchitecture. The DAP and DPC can be used to access AXI-based blocks in your design"
02-04-2021 01:08 PM
I have not used the DPC much yet myself but there are some good details in the TRM Chapter 80
"The DPC is part of the HSDP solution and allowsaccess to all debug resources including Arm CoreSight debug and trace and ChipScope" so Vitis is not a requirement for DPC.
02-05-2021 05:39 AM
From the attached document, Figure 116: Host Debug Port Interfaces, the JTAG is connected to the arm_dap controller, so I suppose I should use Vitis?
Is there any example designs for HSDP with JTAG for versal?
02-08-2021 02:15 AM
For Versal devices, JTAG-AXI functionality can be achieved with CIPS IP. Please enable LPD /FPD (PS-PL interface) while customizing CIPS IP and connect your AXI slave. After programming the PDI, you can select the DPC or A72 targets in XSDB and perform mwr or mrd