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Adventurer
Adventurer
7,784 Views
Registered: ‎06-13-2011

Need help getting Chipscope Pro Inserter to work with ISE 14.1

Hello - 

I have been working with ISE 14.1 for over a year but just a few days ago paid for the full license version with the hopes of getting Chipscope Pro Inserter to help me with my design. Using Windows 7 with Device xc5vlx50-ff1153-3 that is on a board with a 400 Mhz differential clock IC coming into the FPGA that gets programmed with a Xilinx USB II cable via xilinx programmer.  The chip gets the bit file from iMPACT in ISE and I created a Chipscope cdc file in ISE to integrate with my design - see attached xls for the settings for this file. This design does work without Chipscope but a few of the signals coming out for a SPI process are irregular so I would like to see what is going on. I do test bench my HDL processes first and things look good there.

 

- I cannot seem to get Chipscope to start sampling or get the clock to work (it did work with a very small design I had about 6 months ago when I had the eval version) but now it just keeps saying  sampling 0% or slow or stopped clock and never does anything else whether I am doing trigger immediate sampling or trigger regular sampling. I have given my resulting global BUFGDS clock as the clock in Chipscope and listed 4 signals that should be toggleing after the first 100 clock cycles on startup. Note that I did make sure the Keep Hierarchy Order is set to Yes in Synthesis as instructed in the users guide for Chipscope.   I also see that 2 bit files get created in the Generate step of my Implementation steps - I do not know why that is or what to do about it but I get myfile.bit and then about 4 seconds later it creates myfile_cclktemp.bit - both files are the same size 1.533 meg -  why is this happening and what does it mean?

 

The project design before I added the Chipscope Inserter gets no errors and no warnings but informational messages.  I do have my timing constraint on the differential global **bleep** pins coming in as:

 

#Created by Constraints Editor (xc5vlx50-ff1153-3) - 2014/08/11

NET "IO4_N0_D14_GC" TNM_NET = IO4_N0_D14_GC;

TIMESPEC TS_IO4_N0_D14_GC = PERIOD "IO4_N0_D14_GC" 400 MHz HIGH 50% INPUT_JITTER 0.2 ns;

NET "IO4_P0_D15_GC" TNM_NET = IO4_P0_D15_GC;

TIMESPEC TS_IO4_P0_D15_GC = PERIOD "IO4_P0_D15_GC" 400 MHz HIGH 50% INPUT_JITTER 0.2 ns;

 

Informational Messages before Chipscope inserter tool is added:

INFO 

Xst:2679 - Register <DONE_RESETTING> in unit <SCHEMATIC1> has a constant value of 1 during circuit operation. The register is replaced by logic.

 

INFO 

Xst:2679 - Register <CHIP_NO_INST> in unit <ads5400_startup_inst> has a constant value of 1 during circuit operation. The register is replaced by logic.

Clock constraint path messages before adding Chipscope.:

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV1_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV1_inst_1_CLK0_BUF = PERIOD "DCM_ADV1_inst_1_CLK0_BUF" TS_IO4_N0_D14_GC HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV1_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV1 = PERIOD "DCM_CLK_DIV1" TS_IO4_N0_D14_GC / 2 HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV90_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV90_inst_1_CLK0_BUF = PERIOD "DCM_ADV90_inst_1_CLK0_BUF" TS_IO4_N0_D14_GC PHASE 0.625 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV90_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV901 = PERIOD "DCM_CLK_DIV901" TS_IO4_N0_D14_GC / 2 PHASE 0.625 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV180_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV180_inst_1_CLK0_BUF = PERIOD "DCM_ADV180_inst_1_CLK0_BUF" TS_IO4_N0_D14_GC PHASE 1.25 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV180_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV1801 = PERIOD "DCM_CLK_DIV1801" TS_IO4_N0_D14_GC / 2 PHASE 1.25 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV270_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV270_inst_1_CLK0_BUF = PERIOD "DCM_ADV270_inst_1_CLK0_BUF" TS_IO4_N0_D14_GC PHASE 1.875 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_N0_D14_GC', used in period specification 'TS_IO4_N0_D14_GC', was traced into DCM_ADV instance DCM_ADV270_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV2701 = PERIOD "DCM_CLK_DIV2701" TS_IO4_N0_D14_GC / 2 PHASE 1.875 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV1_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV1_inst_1_CLK0_BUF_0 = PERIOD "DCM_ADV1_inst_1_CLK0_BUF_0" TS_IO4_P0_D15_GC HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV1_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV1_0 = PERIOD "DCM_CLK_DIV1_0" TS_IO4_P0_D15_GC / 2 HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV90_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV90_inst_1_CLK0_BUF_0 = PERIOD "DCM_ADV90_inst_1_CLK0_BUF_0" TS_IO4_P0_D15_GC PHASE 0.625 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV90_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV901_0 = PERIOD "DCM_CLK_DIV901_0" TS_IO4_P0_D15_GC / 2 PHASE 0.625 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV180_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV180_inst_1_CLK0_BUF_0 = PERIOD "DCM_ADV180_inst_1_CLK0_BUF_0" TS_IO4_P0_D15_GC PHASE 1.25 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV180_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV1801_0 = PERIOD "DCM_CLK_DIV1801_0" TS_IO4_P0_D15_GC / 2 PHASE 1.25 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV270_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLK0: <TIMESPEC TS_DCM_ADV270_inst_1_CLK0_BUF_0 = PERIOD "DCM_ADV270_inst_1_CLK0_BUF_0" TS_IO4_P0_D15_GC PHASE 1.875 ns HIGH 50% INPUT_JITTER 0.2 ns>

 

INFO 

ConstraintSystem:178 - TNM 'IO4_P0_D15_GC', used in period specification 'TS_IO4_P0_D15_GC', was traced into DCM_ADV instance DCM_ADV270_inst_1/DCM_ADV_INST. The following new TNM groups and period specifications were generated at the DCM_ADV output(s): CLKDV: <TIMESPEC TS_DCM_CLK_DIV2701_0 = PERIOD "DCM_CLK_DIV2701_0" TS_IO4_P0_D15_GC / 2 PHASE 1.875 ns HIGH 50% INPUT_JITTER 0.2 ns>

INFO 

MapLib:562 - No environment variables are currently set.

 

INFO 

LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.

 

INFO 

Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

 

INFO 

Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)

 

INFO 

Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.

 

INFO 

Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp).

 

INFO 

Pack:1650 - Map created a placed design

INFO 

Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".

 

INFO 

Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.

INFO 

Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.

 

INFO 

Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).

 

INFO 

Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.

 

INFO 

Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.

 AFTER Chipscope cdc inserter is added I get:

Device Utilization Summary

[-]

Slice Logic Utilization

Used

Available

Utilization

Note(s)

Number of Slice Registers

632

28,800

2%

 

    Number used as Flip Flops

631

 

 

 

    Number used as Latches

1

 

 

 

Number of Slice LUTs

456

28,800

1%

 

    Number used as logic

388

28,800

1%

 

        Number using O6 output only

337

 

 

 

        Number using O5 output only

50

 

 

 

        Number using O5 and O6

1

 

 

 

    Number used as Memory

57

7,680

1%

 

        Number used as Shift Register

57

 

 

 

            Number using O6 output only

55

 

 

 

            Number using O5 output only

1

 

 

 

            Number using O5 and O6

1

 

 

 

    Number used as exclusive route-thru

11

 

 

 

Number of route-thrus

60

 

 

 

    Number using O6 output only

60

 

 

 

Number of occupied Slices

329

7,200

4%

 

Number of LUT Flip Flop pairs used

776

 

 

 

    Number with an unused Flip Flop

144

776

18%

 

    Number with an unused LUT

320

776

41%

 

    Number of fully used LUT-FF pairs

312

776

40%

 

    Number of unique control sets

65

 

 

 

    Number of slice register sites lost
        to control set restrictions

134

28,800

1%

 

Number of bonded IOBs

214

560

38%

 

    Number of LOCed IOBs

214

214

100%

 

    IOB Master Pads

51

 

 

 

    IOB Slave Pads

51

 

 

 

Number of BlockRAM/FIFO

1

48

2%

 

    Number using BlockRAM only

1

 

 

 

        Number of 18k BlockRAM used

1

 

 

 

    Total Memory used (KB)

18

1,728

1%

 

Number of BUFG/BUFGCTRLs

10

32

31%

 

    Number used as BUFGs

10

 

 

 

Number of BSCANs

1

4

25%

 

Number of DCM_ADVs

4

12

33%

 

Number of ISERDESs

48

 

 

 

Number of OSERDESs

49

 

 

 

    Number of LOCed OSERDESs

4

49

8%

 

Number of RPM macros

9

 

 

 

Average Fanout of Non-Clock Nets

1.93

 

 

 

 

Performance Summary

[-]

Final Timing Score:

0 (Setup: 0, Hold: 0)

Pinout Data&colon;

Pinout Report

Routing Results:

All Signals Completely Routed

Clock Data&colon;

Clock Report

Timing Constraints:

All Constraints Met

 

 

 With Chipscope Inserter CDC file - 75 warnings are added to the implementation mostly dealing with the ICON signal in CHIPSCOPE:

Program

Summary

New

ngdbuild

WARNING 

NgdBuild:486 - Attribute "INIT_FILE" is not allowed on symbol "U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V5.U_CS_BRAM_CASCADE_V5/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb16/U_RAMB16" of type "RAMB16". This attribute will be ignored.

 

map

WARNING 

PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 

map

WARNING 

PhysDesignRules:367 - The signal <U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_V5.U_CS_GANDX_SRL_V5/U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/SRL_Q_O> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<21>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<28>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<33>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<29>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<17>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<34>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<15>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<16>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<35>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<18>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<31>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<32>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<23>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<27>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<10>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<7>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<26>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<11>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<22>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<24>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<30>> is incomplete. The signal does not drive any load pins in the design.

 

map

WARNING 

PhysDesignRules:367 - The signal <icon_control0<25>> is incomplete. The signal does not drive any load pins in the design.

 

par

WARNING 

Par:288 - The signal U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_V5.U_CS_GANDX_SRL_V5/U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/SRL_Q_O has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<21> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<28> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<33> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<29> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<17> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<34> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<15> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<16> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<35> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<18> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<31> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<32> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<23> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<27> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<10> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<7> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<26> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<11> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<22> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<24> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<30> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

Par:288 - The signal icon_control0<25> has no load. PAR will not attempt to route this signal.

 

par

WARNING 

ParHelpers:361 - There are 23 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

 

par

WARNING 

Par:283 - There are 23 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

 

bitgen

WARNING 

PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/U_MU/I_MUT_GANDX.U_match/I_CS_GANDX.U_CS_GANDX_SRL/I_V5.U_CS_GANDX_SRL_V5/U_CS_GAND_SRL_V5/I_USE_RPM_NE0.U_GAND_SRL_SET/SRL_Q_O> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<21>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<28>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<33>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<29>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<17>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<34>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<15>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<16>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<35>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<18>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<31>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<32>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<23>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<27>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<10>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<7>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<26>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<11>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<22>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<24>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<30>> is incomplete. The signal does not drive any load pins in the design.

 

bitgen

WARNING 

PhysDesignRules:367 - The signal <icon_control0<25>> is incomplete. The signal does not drive any load pins in the design.

Chipscope Inserter settings: I have included an attached XLS worksheet that has screen captures of the Chipscope Pro Inserter settings that I made as a reference.

 

 

I then tried using both the JTAG CLK and the CCLK in the Bitgen settings to see if I could get chipscope to work - both settings made no difference.

 

Any suggestions or advice would be greatly appreciated.   

 

Thank you,

-Marc

 

 

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Adventurer
Adventurer
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Registered: ‎06-13-2011

Re: Need help getting Chipscope Pro Inserter to work with ISE 14.1

As another note - here is what the Planahead console says about the ICON ila when I open up Planahead 14.1

 

WARNING:NetListWriters:306 - Signal bus
U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly<4 : 0> on block ila_pro_0 is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus
U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/iDOUT_dly<2 : 0> on block ila_pro_0 is not
reconstructed, because there are some missing bus signals.
WARNING:NetListWriters:306 - Signal bus U0/U_ICON/iCORE_ID_SEL<15 : 0> on block
icon_pro is not reconstructed, because there are some missing bus signals.
finished :Prep

 

Yet, I do see the ICON_pro and ila_pro_0 nets list in  planahead.

 

-Marc

 

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