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Visitor hai_tran
Visitor
5,009 Views
Registered: ‎05-04-2017

Post Route Logic Modification

Hi all,

 

I would like some guidance on how to perform post route logic modification on an Artix 7 design using Vivado 2014.3.1. I only needed to invert a signal. My goal is to preserve the known good routing and only affect one output signal with this change.

 

I appreciate all your inputs.

 

Hai Tran

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7 Replies
Moderator
Moderator
5,004 Views
Registered: ‎06-05-2013

Re: Post Route Logic Modification

Check Page#83 of the following user guide
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_3/ug904-vivado-implementation.pdf

You can use incremental compile option.
Thanks
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Historian
Historian
4,996 Views
Registered: ‎01-23-2009

Re: Post Route Logic Modification

Vivado has fairly extensive capabilities for "Engineering Change Order (ECO)" changes - the ability to make minor changes to the design after it has been placed and routed.

 

This is done with commands like

  - create_cell

  - remove_cell

  - create_net

  - connect_net

  - (and some others)

 

With these you can change the structure of your design.

 

Then, each cell can be configured via its properties using

 

set_property <property> <value> [get_cells <cell>]

 

Once the structural changes are made, you need to route any new/modified nets, which is done with route_design - it will only route unrouted nets, or nets that it needs to move out of the way for the new nets (or you can override the latter with the -preserve option).

 

However, for simple inversion, you may be able to do it just by changing properties - depending on what you need to invert. Inverting an input at  a LUT is a matter of changing the LUT truth table - this can be done using the

 

set_property INIT <new_value> [get_cells <cell name>]

 

The INIT is a 64 bit (for a LUT6) value that represents the truth table of the LUT. I am sure there is documentation somewhere as to how to create the string, but it is a pretty simple format (probably bit 0 is the output value for the inputs 000000, but 1 for 000001, etc...)

 

Note that this isn't intended to be done in project mode (but you can cheat).

 

In non-project mode, you load the routed .dcp file (using read_checkpoint), make the changes and then write a new .dcp file (using write_checkpoint).

 

In Project mode, you aren't really supposed to do this, but you can fake it by "breaking" the project flow. WARNING - once you do this, your project structure is corrupt (or at least will not reflect your changes, and may overwrite them in the future). However, to do so, you can open the implemented design, make your changes, and then do a write_checkpoint (ideally to a directory outside the project directory structure). You will then have to treat this new checkpoint as a non-project batch checkpoint.

 

Avrum

Visitor hai_tran
Visitor
4,953 Views
Registered: ‎05-04-2017

Re: Post Route Logic Modification

Hi Harshit,

 

That is one elegant way to make changes that preserves most of the reference design place and route.  However, I am looking for more precise changes and that warrants no change to the reference place and route that are not involved in the modification i.e. the one suggested by avrumw.

 

Thanks.

 

Hai

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Moderator
Moderator
4,946 Views
Registered: ‎06-05-2013

Re: Post Route Logic Modification

For more info on ECO flow check the following user guide
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug904-vivado-implementation.pdf
page #142 and for analysis watch the video
https://www.xilinx.com/video/hardware/vivado-engineering-change-order.html

In case you want to test the example design check this out
lab 4
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug986-vivado-tutorial-implementation.pdf

Thanks
Harshit
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Visitor hai_tran
Visitor
4,937 Views
Registered: ‎05-04-2017

Re: Post Route Logic Modification

Hi Avrum,

 

Thank you for a wonderful reply. I have been relying on the Vivado GUI for most of my work. This guidance will help motivate me to use the command base approach (Tcl scripting). I will try out your suggestion.

 

The actual change I wanted to make is as follows:

 

Current Design:

 

1. Net X1 is connected to pin I of IOBxx.OUTBUF    // Input pin of an OUTBUF at IOBxx

 

Desired change:

1. Remove net X1 from pin I

2. Invert net X1 => create net X1_INV

3. Connect net X1_INV to pin T of IOBxx.OUTBUF    // Tristate pin of an OUTBUF at IOBxx

 

I appreciate your help.

 

Hai Tran

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Visitor hai_tran
Visitor
4,615 Views
Registered: ‎05-04-2017

Re: Post Route Logic Modification

Hi Harshit and Avrum,

 

I finally got the changes I wanted using post route Tcl commands Avrum suggested. I got it to work with Vivado 2014.3.1.

 

I made all my changes from the post-route checkpoint file. Here is the resulting Tcl script:

 

set_property INIT 4'h7 [get_cells Arxcis3_i/smbus/inst/I2C_DATA_SEND/h_sda_out_INST_0]    # invert signal by changing truth table
disconnect_net -net {hi_sda_out_wr} -objects [list {HI_SDA_OUT_N_INST_0/T}]                      # remove net from T pin of OBUFT
disconnect_net -net {<const1>} -objects [list {HI_SDA_OUT_N_INST_0/I}]                               # remove net from I pin of OBUFT
connect_net -net {hi_sda_out_wr} -objects [list {HI_SDA_OUT_N_INST_0/I}]                           # connect modified net to I pin of OBUFT
connect_net -net {<const1>} -objects [list {HI_SDA_OUT_N_INST_0/T}]                                 # connect modified net to T pin  of OBUFT
place_design                                                                                                                               # place design
route_design -preserve                                                           # route modified nets while preserving routing of unchanged nets

Moderator
Moderator
4,544 Views
Registered: ‎07-01-2015

Re: Post Route Logic Modification

Hi @hai_tran,

 

Can you please close the thread by marking appropriate reply as solution?

Thanks,
Arpan
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