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Visitor
Visitor
918 Views
Registered: ‎08-02-2018

Power issue -- junction temp exceeded and thermal margin is negative

I have been using vivado 2018.2 for implementing my design. The device is xcvu9p-fsgd2104-2L-e that is also used on the VCU1525 board. The resource ultilization (mainly LUT and FF) is very high. The main clock is required to work at more than 600MHz. The clock is generated by the internal MMCM module. The initial clock frequency is 350MHz and will be configured at 600MHz through DRP port after power on. There is the constraint of 1.5 ns period related to this clock in the XDC file. As shown in the figure, the power report shows that the thermal margin is negative. It seems that the estimated power is out of range in which device can work normally.

Why there is this kind of error? Is there the certain limit in using the large scale FPGA? Must I solve this error? 

 

power issue.jpg

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Xilinx Employee
Xilinx Employee
913 Views
Registered: ‎05-22-2018

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Visitor
Visitor
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Registered: ‎08-02-2018

Thanks. But, In my design, the clock frequency is required to as high as possible. In addition,the power is mainly consumed by the core calculation block that works all the time after power on. Therefore, the clock enable signal is not needed. Then, how do I solve this problem? Is the estimated power related to the constraint value of 1.5ns in the XDC file?
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